CA1162667A - Bandwidth reduction method and structure for combining voice and data in a pcm channel - Google Patents
Bandwidth reduction method and structure for combining voice and data in a pcm channelInfo
- Publication number
- CA1162667A CA1162667A CA000388436A CA388436A CA1162667A CA 1162667 A CA1162667 A CA 1162667A CA 000388436 A CA000388436 A CA 000388436A CA 388436 A CA388436 A CA 388436A CA 1162667 A CA1162667 A CA 1162667A
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- CA
- Canada
- Prior art keywords
- voice
- data
- information
- analog
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1682—Allocation of channels according to the instantaneous demands of the users, e.g. concentrated multiplexers, statistical multiplexers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
- H04M11/06—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
- Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
Abstract
ABSTRACT
Disclosed is a method and structure for the simultaneous trans-mission of voice and data information over the same PCM transmission channel.
In the present invention, analog voice information is sampled at a first sampling rate, during periods when voice information is to be transmitted at a frequency which provides a digitized voice rate equal to the trans-mission rate capability of the transmission channel. During periods when both voice and data are to be transmitted, the analog voice information is sampled at a second sampling rate less then the first sampling rate, thus allowing the merged voice and data information to have a total digitized transmission rate equal to the transmission rate capability of the trans-mission channel.
Disclosed is a method and structure for the simultaneous trans-mission of voice and data information over the same PCM transmission channel.
In the present invention, analog voice information is sampled at a first sampling rate, during periods when voice information is to be transmitted at a frequency which provides a digitized voice rate equal to the trans-mission rate capability of the transmission channel. During periods when both voice and data are to be transmitted, the analog voice information is sampled at a second sampling rate less then the first sampling rate, thus allowing the merged voice and data information to have a total digitized transmission rate equal to the transmission rate capability of the trans-mission channel.
Description
3Vishwas R. Godbole 7 Field of the Invention 9 This invention relates to communication systems, and more specifically to a system capable of transmitting 11 voice information and data information over a single pulse 12 code modulation channel.
14 Description of the Prior Art 16 Systems employing pulse code modulation (PCM) are 17 well-known in the prior art. For example, telephone 18 communication systems often utilize pulse code modulation, 19 in which an analog voice signal is converted to a series of binary pulses. Such telephone communication systems 2L utilize a fixed sampling rate, commonly eight (8) kilo-22 hertz. By converting the sampled speech signal to an 23 eight (8) bit word, the digitized speech is transmitted by 24 pulse code modulation at 64 kilobits per second. Prior art speech transmission utilizes a fixed sampling rate, 26 due to the fact that prior art filters utilize RC circuits 27 to provide the filter characteristics. Utilizing fixed 28 resistors and capacitors, the characteristics of prior art 29 filters are also fixed.
31 Data transmission, such as from a computer or micro-32 processor, also utilizes a series of binary pulses. One 33 common data transmission rate is 9.6 kilobits per second.
Prior art methods of transmitting both speech and 36 data reguire either separate voice and data transmission 37 channels, or a single channel of increased bandwidth
14 Description of the Prior Art 16 Systems employing pulse code modulation (PCM) are 17 well-known in the prior art. For example, telephone 18 communication systems often utilize pulse code modulation, 19 in which an analog voice signal is converted to a series of binary pulses. Such telephone communication systems 2L utilize a fixed sampling rate, commonly eight (8) kilo-22 hertz. By converting the sampled speech signal to an 23 eight (8) bit word, the digitized speech is transmitted by 24 pulse code modulation at 64 kilobits per second. Prior art speech transmission utilizes a fixed sampling rate, 26 due to the fact that prior art filters utilize RC circuits 27 to provide the filter characteristics. Utilizing fixed 28 resistors and capacitors, the characteristics of prior art 29 filters are also fixed.
31 Data transmission, such as from a computer or micro-32 processor, also utilizes a series of binary pulses. One 33 common data transmission rate is 9.6 kilobits per second.
Prior art methods of transmitting both speech and 36 data reguire either separate voice and data transmission 37 channels, or a single channel of increased bandwidth
-2- ll 62667 l capable of carrying both data and speech. Thus, for a 2 voice transmission of 64 kilobits per second to be com-
3 bined with a data transmission of 9.6 kilobits per second,
4 a transmission channel capable of carrying 73.6 kilobits per second is required. In many instances this is not 6 practical or possible. For example, standard PCM channels 7 and equipment are designed to be capable of handling 64 8 kilobits per second, and it is not possible to transmit 9 information in excess of this rate, without redesigning the receiving equipment.
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14 This invention utilizes a unique technique, wherein a single voice channel capable of carrying 64 kilobits per 16 second may be utilized to carry either voice information, 17 data information, or a combination of voice information 18 and data information. This is accomplished by utilizing a 19 unique dual sample rate for the voice information involv-ing a first sampling rate when only voice information is 21 to be transmitted and a second, lower, sampling rate when 22 both voice and data information is to be transmitted.
24 Thus in one embodiment a sampling rate of eight (8) kilohertz is used to provide a pulse code modulated voice 26 signal of 64 kilobits per second during the interval when 27 voice information is transmitted while during the periods 28~ when a combination of voice information and data informa-29 tion (or data information alone) is transmitted, a voice sampling rate of 6.8 kilohertz is utilized, resulting in a 31 digitzed voice rate of 54.4 kilobits per second. This 32 54.4 kilobits per second voice rate allows the addition of 33 data information, at a rate of 9.6 kilobits per second, 34 thus allowing simultaneous voice information and data information transmission over a single 64 kilobits per 36 second pulse code modulation voice channel. The reduction 37 in voice bandwidth from 3.4 kilohertz to 2.9 kilohertz 1 ~ 6266~
during data transmlssion periods does not degrade speech quality signifi-cantly, thus allowing transmission of high quality speech and data informat-ion simultaneously over a standard 64 Kilobit/sec telephone system.
BRIEF DESCRIPTION OF THE DRAWING
Figure 1 is a block diagram of one embodiment of a circuit con-structed in accordance with this invention.
Figure 2a is a graphical representation of the relationship of data information and voice information in a single transmission frame.
Figure 2b is a graphical representation of a synchronizing signal for use in accordance with this invention.
Figure 2c is another representation of the relationship of data information and voice information in a single transmission frame.
Figure 2d illustrates the relationship of a single data byte and a single voice byte to their component bits.
Figure 2e shows the pulse code modulated voice information.
Figure 2f shows continuous serial data information.
Figure 3 is a block diagram of an alternative embodiment of the circuit of this invention as depicted in Figure 1.
Figure 4 is a block diagram of an alternative embodiment of the circuit of this invention as depicted in Figure 3.
DETAILED ~ESCRI~TION OF THE INVENTION
A block diagram of a system capable of allowing simultaneous trans-mission of data information and voice information is shown in Figure 1.
During the periods of "full voice" operation, when voice information is transmitted without the simultaneous transmission of data information, a voice signal is input via lead 30 to pulse code modulator 8. Pulse code modulator, or "encoder", 8 is comprised of filter 20, and analog-to-digital 1 ~ 62667 converter 2:L. A device which may b~ used as encoder 8 i9 manufactured by American Microsystems, Inc., and bears their device number S3501. ~he pulse code modulation output from encoder 8 is then connected to output lead 32, ~hich is connected to the switching network via a PCM transmission channel (not shown). Switches 41 and 42 allow this puise code modulated output from encoder 8 to be directly applied to output lead 32, therefore bypassing various components contained within voicejdata combiner 10. Output lead 32 is connected to the PCM transmission channel ~now shownj.
Also, during the full voice operation, receiver lead 33 is connect-ed via switch 40 and switch 43 to pulse code modulation decoder 9, comprising digital-to-analog converter 22 and filter 23. Decoder Y may comprise an S3502, also manufactured by American Microsystems, Inc. ~he output signal from decoder 9 is applied via bus 36 to a suitable transducer device (not shown) to provide an audible output for human use. The sampling rate for encoding and decoding the voice signal during the full-voice mode is prefer-ably 8 kilohertz, thus allowing the transmission of 80U0 8-bit words per second over the standard 64 kilobit/sec PCM channel.
A synchronization ("sync") signal is generated by the local switch-ing network (not shown) in a well-known manner, and made available to voice/
data combiner 10 via input line 31. In one preferred embodiment, this sync signal has a frequency of 400 hertz, and a 15% duty cycle. Other sync signals may be used as required for specific system performance. ~his sync signal is connected to phase lock loop 1 which locks on to the sync signal, and provides various clock references for controlling voice/data combiner 10, encoder 8 and decoder 9.
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_5_ ~1 62~67 , 1 During the periods when both voice information and 2 data information are to transmitted simultaneously ("voice/
3 data mode"), switches 40, 41, 42, and 43 are opened, thus 4 inserting various system elements in the path between encoder 8 and switch interface lead 32, and the path 6 between switch interface lead 33 and decoder 9. During 7 the reception of a voice/data signal, the PCM signal is 8 received via switch interface lead 33. The serial data 9 stream is fed to serial-to-parallel register 12, which provides an output 8 bits wide. A device which may be 11 used as a serial-to-parallel register is the SN74164, 12 manufactured by Texas Instruments, Inc. This parallel 13 output signal from serial-to-parallel register 12 is 14 connected to demultiplexor 18. Demultiplexor 18 is clocked by a signal made available from phase lock loop 1, 16 such that during the reception of the data portion of the 17 PCM input signal, the parallel output from register 12 is 18 connected by demultiplexor 18 to receive-data-buffer 15, 19 and during the reception of the voice portion of PCM input signal, the output from register 12 is connected by 21 demultiplexor 18 to receive-voice-buffer 14. For the 22 system described, the sync signal depicted in Figure 2b is 23 high during the first three (3) bytes, which are the data 24 bytes. Thus, this 400 Hz, 15% duty cycle sync signal is used to control multiplexor 7 and demultiplexor 18 such 26 that data information is transmitted and received during 27 the first three (3) bytes of each frame, and analog infor-28 mation is transmitted and received during the remaining 29 seventeen (17) bytes per frame. For a system where three 8-bit data bytes are transmitted per frame, receive-data-31 buffer 15 is a 3 word by 8 bit memory. Similarly, for a 32 system where 17 8-bit voice bytes are transmitted in a 33 single frame, receive voice buffer 14 is a 17 word by 8 34 bit memory. For the system employing 17 words per 2.5 msec frame during the voice/data mode, encoder 8 and 36 decoder 9 operate at 6.8 KHz, resulting in a digitized 37 voice rate of 54.4 kilobits/sec.
1 1 626~7 During the receptlon of a volce/data signal, each frame has a period of 2.5 mS, as shown in Figure 2a. Since each frame contains 20 bytes, each byte is transmitted in 125 microseconds. Thus, an 8-bit byte is output from serial-to-parallel register 12 every 125 microseconds. Each data byte is clocked into data buffer 15 at the rate of one byte per 125 microseconds, although only ~ data bytes are input during each frame, as shown in Figure 2c.
Similarly, each voice byte is shifted into voice buffer 14 in 125 microseconds, although only 17 voice bytes are shifted per frame. A sync signal (shown in Figure 2b), available from local switching equipment ~not shownj has a frequ-ency of 400 Hz and a 15% duty cycle. Thus the sync signal is high during the flrst three bytes of each frame, which corresponds to the data bytes, thus allowing multiplexor 7 and demultiplexor 18 to selectively interface with voice buffers 4 and 14, and data buffers 5 and 15, as required. Multiplexor 7 may comprise two SN74157 devices manufactured, for example, by Texas Instruments, Inc. and demultiplexor 18 may comprise two SN74LS244 devices, manufactured, for example, by Texas Instruments, Inc.
Each voice and data byte is comprised of 8 bits as shown in Figure 2d. The data is shifted out of data buffer 15 at the rate of approximately 83~ microseconds/byte, or three bytes per frame, thereby providing a continu-ous stream of data output, as shown in Figure 2F. This 83~ microseconds/byte clock signal, as well as all other clock signals used to control the various buffers, registers, multiplexors, demultiplexors, encoders and decoders are generated by phase lock loop 1 ln a well-known manner. Phase lock loop uses the sync signal, as depicted in Figure 2b, as a reference, thereby providing accurate clock signals for the operation of the system. This data output is connected through interface and control loglc 6 to a data receiver (not shownJ
having a microprocessor interface 35 and a data I/0 interface 34. Similarly, voice information is shifted out of voice buffer 14 at approximately 147 microseconds per byte, or 17 bytes per frame, via a paraliel~to-serial re-gister 3 thus providing a contimlous stream of voice information to decoder 9, as shown in Figure 2e. This continuous stream is desired to provide high quality voice transmission. If, on the other hand, the voice sampllng rate remains constant, and during the voice~data mode three (3) voice bytes are replaced by three (3) data bytes during each frame, three (3~ voice bytes per frame will be lost, resulting in a noticeable degradatlon in quallty of the transmitted voice signal.
In a similar fashion, voice information is received via lead 30 of encoder 8, for sampling at approximately 147 microseconds per byte during the voice/data mlode. ~his information is fed to serlal-to-parallel register 2, which converts the serial stream of bits from encoder 8 to a parallel stream of information, 8 bits wide. The parallel voice information from register 2 is clocked into transmit voice buffer 4 at approximately 147 microseconds per byte. Voice buffer 4 is a 17 word by 8 bit memory. Data information is received from a data terminal (not shown) through interface and control logic 6 to transmit data buffer 5, at approximately 833 microseconds per byte. Trans-mit data buffer 5 is a 3 word by 8 bit memory. Voice information and data information are clocked out of buffers 4 and 5 at 125 microseconds per byte.
During the first 3 bytes per frame, data is clocked out of data buffer 5, through multiplexor 7, and to parallel-to-serial register 13. During the re-maining 17 bytes per frame, voice information is shifted out of voice buffer 4, through multiplexor 7 to parallel-to-serial register 13. Parallel-to-serial register 13 converts an 8 bit wide byte into a continuous stream of binary data which is connected to switch interface lead 32 and transmitted over a standard 64 kilobit/sec PCM channel.
This invention also includes a method of queuing each station in a ,'~'~'''' -i 1 62667 comm~mications network, such that each station is either in the full voice mode, or the voice/data mode, as required. When in the full voice mode, a unique audible or subaudible tone (or set of tones) is transmitted by a first station to each associated station in communication with the first station, over the same PCM transmission channel used to transmit voice and data infor-mation, in order to signal all associated stations to switch to the voice/data mode. With stations in the voice/data mode, the same or a different tone may be transmitted over the PCM channel by one station to signal all associated stations to switch to the full voice mode. Such a tone, or set of tones, is generated by tone generator 100, of well-known design, as shown in Figure 1, and then applied to pulse code modulator 8. 'l~he transmitted tone is detected by the tone decoder 101 of the receiving voice/data combiner, and a signal applied to interface and control logic 6, which then causes the receiving voice/
data combiner 10 to enter the voice/data mode.
Alternatively, a special binary word, or set of words, represent-ative of a queuing tone, or set of tones, is transmitted by one station to signal a change from the voice/data mode to the full voice mode. Thus, Figure 3 shows an alternative embodiment of the voice/data combiner 10 of the present invention. Those elements of the circuit of ~igure 3 common to the elements of the circuit of Figure 1 are designated by the same reference numeral. In the alternative embodiment depicted in Figure 3, the special binary word, or set of words, representing queuing tone signals are stored in PCM form in a read only memory queuing ROM 110 in voice/data combiner 10, and applied to parallel-to-serial register 13 as needed to be transmitted as a voice signal, as control-led by interface and control logic 6.
In Figure 4 which shows an alternative embodiment of the voice/data combiner 10 of Figures 1 and 3, those elements common to the circuits of Figures 1 and 3 are designated by the same reference numerals. In this ~ ' alternative embodiment, a unique data word, or set of words, are stored in ROM 110 contained within the voice/data combiner 10, and transmltted as a data signal as required to signal a transition from the voice/data mode to the full voice mode. This data signal is decoded by interface and control logic 6, which then switches voice/data combiner 10 to the ~ull voice mode. These alternative, binary queuing signals are also transmitted over the same PCM
channel used to ~ransmit voice and data ~nformation, -8a-..
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9 ~ ~ 62667 1 thus eliminating the need for an additional, independent 2 queuing channel. The binary queuing signals must be 3 selected in a manner that is compatible with the sampling 4 rate of the system. For example, if the binary queuing signal is to be transmitted as a voice signal, it must 6 have the same format (i.e., same number of bits, and the 7 same transmission rate) as the voice signals. In a similar 8 manner, if the binary queuing signal is to be transmitted 9 as a data signal, it must have the same format as a data signal.
12 The embodiments described in this specification are 13 illustrative only. Many other embodiments are capable of 14 being formed using the principles of this invention.
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14 This invention utilizes a unique technique, wherein a single voice channel capable of carrying 64 kilobits per 16 second may be utilized to carry either voice information, 17 data information, or a combination of voice information 18 and data information. This is accomplished by utilizing a 19 unique dual sample rate for the voice information involv-ing a first sampling rate when only voice information is 21 to be transmitted and a second, lower, sampling rate when 22 both voice and data information is to be transmitted.
24 Thus in one embodiment a sampling rate of eight (8) kilohertz is used to provide a pulse code modulated voice 26 signal of 64 kilobits per second during the interval when 27 voice information is transmitted while during the periods 28~ when a combination of voice information and data informa-29 tion (or data information alone) is transmitted, a voice sampling rate of 6.8 kilohertz is utilized, resulting in a 31 digitzed voice rate of 54.4 kilobits per second. This 32 54.4 kilobits per second voice rate allows the addition of 33 data information, at a rate of 9.6 kilobits per second, 34 thus allowing simultaneous voice information and data information transmission over a single 64 kilobits per 36 second pulse code modulation voice channel. The reduction 37 in voice bandwidth from 3.4 kilohertz to 2.9 kilohertz 1 ~ 6266~
during data transmlssion periods does not degrade speech quality signifi-cantly, thus allowing transmission of high quality speech and data informat-ion simultaneously over a standard 64 Kilobit/sec telephone system.
BRIEF DESCRIPTION OF THE DRAWING
Figure 1 is a block diagram of one embodiment of a circuit con-structed in accordance with this invention.
Figure 2a is a graphical representation of the relationship of data information and voice information in a single transmission frame.
Figure 2b is a graphical representation of a synchronizing signal for use in accordance with this invention.
Figure 2c is another representation of the relationship of data information and voice information in a single transmission frame.
Figure 2d illustrates the relationship of a single data byte and a single voice byte to their component bits.
Figure 2e shows the pulse code modulated voice information.
Figure 2f shows continuous serial data information.
Figure 3 is a block diagram of an alternative embodiment of the circuit of this invention as depicted in Figure 1.
Figure 4 is a block diagram of an alternative embodiment of the circuit of this invention as depicted in Figure 3.
DETAILED ~ESCRI~TION OF THE INVENTION
A block diagram of a system capable of allowing simultaneous trans-mission of data information and voice information is shown in Figure 1.
During the periods of "full voice" operation, when voice information is transmitted without the simultaneous transmission of data information, a voice signal is input via lead 30 to pulse code modulator 8. Pulse code modulator, or "encoder", 8 is comprised of filter 20, and analog-to-digital 1 ~ 62667 converter 2:L. A device which may b~ used as encoder 8 i9 manufactured by American Microsystems, Inc., and bears their device number S3501. ~he pulse code modulation output from encoder 8 is then connected to output lead 32, ~hich is connected to the switching network via a PCM transmission channel (not shown). Switches 41 and 42 allow this puise code modulated output from encoder 8 to be directly applied to output lead 32, therefore bypassing various components contained within voicejdata combiner 10. Output lead 32 is connected to the PCM transmission channel ~now shownj.
Also, during the full voice operation, receiver lead 33 is connect-ed via switch 40 and switch 43 to pulse code modulation decoder 9, comprising digital-to-analog converter 22 and filter 23. Decoder Y may comprise an S3502, also manufactured by American Microsystems, Inc. ~he output signal from decoder 9 is applied via bus 36 to a suitable transducer device (not shown) to provide an audible output for human use. The sampling rate for encoding and decoding the voice signal during the full-voice mode is prefer-ably 8 kilohertz, thus allowing the transmission of 80U0 8-bit words per second over the standard 64 kilobit/sec PCM channel.
A synchronization ("sync") signal is generated by the local switch-ing network (not shown) in a well-known manner, and made available to voice/
data combiner 10 via input line 31. In one preferred embodiment, this sync signal has a frequency of 400 hertz, and a 15% duty cycle. Other sync signals may be used as required for specific system performance. ~his sync signal is connected to phase lock loop 1 which locks on to the sync signal, and provides various clock references for controlling voice/data combiner 10, encoder 8 and decoder 9.
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_5_ ~1 62~67 , 1 During the periods when both voice information and 2 data information are to transmitted simultaneously ("voice/
3 data mode"), switches 40, 41, 42, and 43 are opened, thus 4 inserting various system elements in the path between encoder 8 and switch interface lead 32, and the path 6 between switch interface lead 33 and decoder 9. During 7 the reception of a voice/data signal, the PCM signal is 8 received via switch interface lead 33. The serial data 9 stream is fed to serial-to-parallel register 12, which provides an output 8 bits wide. A device which may be 11 used as a serial-to-parallel register is the SN74164, 12 manufactured by Texas Instruments, Inc. This parallel 13 output signal from serial-to-parallel register 12 is 14 connected to demultiplexor 18. Demultiplexor 18 is clocked by a signal made available from phase lock loop 1, 16 such that during the reception of the data portion of the 17 PCM input signal, the parallel output from register 12 is 18 connected by demultiplexor 18 to receive-data-buffer 15, 19 and during the reception of the voice portion of PCM input signal, the output from register 12 is connected by 21 demultiplexor 18 to receive-voice-buffer 14. For the 22 system described, the sync signal depicted in Figure 2b is 23 high during the first three (3) bytes, which are the data 24 bytes. Thus, this 400 Hz, 15% duty cycle sync signal is used to control multiplexor 7 and demultiplexor 18 such 26 that data information is transmitted and received during 27 the first three (3) bytes of each frame, and analog infor-28 mation is transmitted and received during the remaining 29 seventeen (17) bytes per frame. For a system where three 8-bit data bytes are transmitted per frame, receive-data-31 buffer 15 is a 3 word by 8 bit memory. Similarly, for a 32 system where 17 8-bit voice bytes are transmitted in a 33 single frame, receive voice buffer 14 is a 17 word by 8 34 bit memory. For the system employing 17 words per 2.5 msec frame during the voice/data mode, encoder 8 and 36 decoder 9 operate at 6.8 KHz, resulting in a digitized 37 voice rate of 54.4 kilobits/sec.
1 1 626~7 During the receptlon of a volce/data signal, each frame has a period of 2.5 mS, as shown in Figure 2a. Since each frame contains 20 bytes, each byte is transmitted in 125 microseconds. Thus, an 8-bit byte is output from serial-to-parallel register 12 every 125 microseconds. Each data byte is clocked into data buffer 15 at the rate of one byte per 125 microseconds, although only ~ data bytes are input during each frame, as shown in Figure 2c.
Similarly, each voice byte is shifted into voice buffer 14 in 125 microseconds, although only 17 voice bytes are shifted per frame. A sync signal (shown in Figure 2b), available from local switching equipment ~not shownj has a frequ-ency of 400 Hz and a 15% duty cycle. Thus the sync signal is high during the flrst three bytes of each frame, which corresponds to the data bytes, thus allowing multiplexor 7 and demultiplexor 18 to selectively interface with voice buffers 4 and 14, and data buffers 5 and 15, as required. Multiplexor 7 may comprise two SN74157 devices manufactured, for example, by Texas Instruments, Inc. and demultiplexor 18 may comprise two SN74LS244 devices, manufactured, for example, by Texas Instruments, Inc.
Each voice and data byte is comprised of 8 bits as shown in Figure 2d. The data is shifted out of data buffer 15 at the rate of approximately 83~ microseconds/byte, or three bytes per frame, thereby providing a continu-ous stream of data output, as shown in Figure 2F. This 83~ microseconds/byte clock signal, as well as all other clock signals used to control the various buffers, registers, multiplexors, demultiplexors, encoders and decoders are generated by phase lock loop 1 ln a well-known manner. Phase lock loop uses the sync signal, as depicted in Figure 2b, as a reference, thereby providing accurate clock signals for the operation of the system. This data output is connected through interface and control loglc 6 to a data receiver (not shownJ
having a microprocessor interface 35 and a data I/0 interface 34. Similarly, voice information is shifted out of voice buffer 14 at approximately 147 microseconds per byte, or 17 bytes per frame, via a paraliel~to-serial re-gister 3 thus providing a contimlous stream of voice information to decoder 9, as shown in Figure 2e. This continuous stream is desired to provide high quality voice transmission. If, on the other hand, the voice sampllng rate remains constant, and during the voice~data mode three (3) voice bytes are replaced by three (3) data bytes during each frame, three (3~ voice bytes per frame will be lost, resulting in a noticeable degradatlon in quallty of the transmitted voice signal.
In a similar fashion, voice information is received via lead 30 of encoder 8, for sampling at approximately 147 microseconds per byte during the voice/data mlode. ~his information is fed to serlal-to-parallel register 2, which converts the serial stream of bits from encoder 8 to a parallel stream of information, 8 bits wide. The parallel voice information from register 2 is clocked into transmit voice buffer 4 at approximately 147 microseconds per byte. Voice buffer 4 is a 17 word by 8 bit memory. Data information is received from a data terminal (not shown) through interface and control logic 6 to transmit data buffer 5, at approximately 833 microseconds per byte. Trans-mit data buffer 5 is a 3 word by 8 bit memory. Voice information and data information are clocked out of buffers 4 and 5 at 125 microseconds per byte.
During the first 3 bytes per frame, data is clocked out of data buffer 5, through multiplexor 7, and to parallel-to-serial register 13. During the re-maining 17 bytes per frame, voice information is shifted out of voice buffer 4, through multiplexor 7 to parallel-to-serial register 13. Parallel-to-serial register 13 converts an 8 bit wide byte into a continuous stream of binary data which is connected to switch interface lead 32 and transmitted over a standard 64 kilobit/sec PCM channel.
This invention also includes a method of queuing each station in a ,'~'~'''' -i 1 62667 comm~mications network, such that each station is either in the full voice mode, or the voice/data mode, as required. When in the full voice mode, a unique audible or subaudible tone (or set of tones) is transmitted by a first station to each associated station in communication with the first station, over the same PCM transmission channel used to transmit voice and data infor-mation, in order to signal all associated stations to switch to the voice/data mode. With stations in the voice/data mode, the same or a different tone may be transmitted over the PCM channel by one station to signal all associated stations to switch to the full voice mode. Such a tone, or set of tones, is generated by tone generator 100, of well-known design, as shown in Figure 1, and then applied to pulse code modulator 8. 'l~he transmitted tone is detected by the tone decoder 101 of the receiving voice/data combiner, and a signal applied to interface and control logic 6, which then causes the receiving voice/
data combiner 10 to enter the voice/data mode.
Alternatively, a special binary word, or set of words, represent-ative of a queuing tone, or set of tones, is transmitted by one station to signal a change from the voice/data mode to the full voice mode. Thus, Figure 3 shows an alternative embodiment of the voice/data combiner 10 of the present invention. Those elements of the circuit of ~igure 3 common to the elements of the circuit of Figure 1 are designated by the same reference numeral. In the alternative embodiment depicted in Figure 3, the special binary word, or set of words, representing queuing tone signals are stored in PCM form in a read only memory queuing ROM 110 in voice/data combiner 10, and applied to parallel-to-serial register 13 as needed to be transmitted as a voice signal, as control-led by interface and control logic 6.
In Figure 4 which shows an alternative embodiment of the voice/data combiner 10 of Figures 1 and 3, those elements common to the circuits of Figures 1 and 3 are designated by the same reference numerals. In this ~ ' alternative embodiment, a unique data word, or set of words, are stored in ROM 110 contained within the voice/data combiner 10, and transmltted as a data signal as required to signal a transition from the voice/data mode to the full voice mode. This data signal is decoded by interface and control logic 6, which then switches voice/data combiner 10 to the ~ull voice mode. These alternative, binary queuing signals are also transmitted over the same PCM
channel used to ~ransmit voice and data ~nformation, -8a-..
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9 ~ ~ 62667 1 thus eliminating the need for an additional, independent 2 queuing channel. The binary queuing signals must be 3 selected in a manner that is compatible with the sampling 4 rate of the system. For example, if the binary queuing signal is to be transmitted as a voice signal, it must 6 have the same format (i.e., same number of bits, and the 7 same transmission rate) as the voice signals. In a similar 8 manner, if the binary queuing signal is to be transmitted 9 as a data signal, it must have the same format as a data signal.
12 The embodiments described in this specification are 13 illustrative only. Many other embodiments are capable of 14 being formed using the principles of this invention.
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Claims (11)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. The method of transmitting a voice signal and data information on a single channel comprising:
(a) sampling the voice signal at a first rate in the absence of data to be transmitted; and (b) sampling the voice signal at a second rate, lower than said first rate, and sampling the data information at a third rate lower than said first rate, during the presence of data to be transmitted.
(a) sampling the voice signal at a first rate in the absence of data to be transmitted; and (b) sampling the voice signal at a second rate, lower than said first rate, and sampling the data information at a third rate lower than said first rate, during the presence of data to be transmitted.
2. The method of Claim 1 wherein the combined sampling rate of said voice signal and said data information during the presence of data to be transmitted is equal to the sampling rate of said voice signal during the absence of data to be transmitted.
3. The structure for transmitting a voice signal and data information on a single channel comprising: means for sampling the voice signal at a first rate in the absence of data to be transmitted; and means for sampling the voice signal at a second rate, lower than said first rate, and sampling the data information at a third rate lower than said first rate, during the presence of data to be transmitted.
4. The structure of Claim 3 wherein the combined sampling rate of said voice signal and said data information during the presence of data to be trans-mitted is equal to the sampling rate of said voice signal during the absence of data to be transmitted.
5. The method of transmitting a voice signal and data information on a single channel comprising the steps of:
(a) pulse code modulating said voice signal at a first sampling rate into a series of voice frames during periods when only voice information is to be transmitted, each said voice frame comprising a plurality of voice bytes;
(b) pulse code modulating said voice signal at a second sampling rate less than said first sampling rate into a series of voice frames during periods when both voice information and data information is to be transmitted, each said voice frame comprising a plurality of voice bytes;
(c) merging one or more data bytes with one or more voice bytes to form a voice/data frame during periods when both voice information and data information are to be transmitted, thereby forming a series of voice/data frames comprising both voice bytes and data bytes;
{d) transmitting said voice frames to a receiving location during periods when voice information only is to be transmitted;
(e) transmitting said voice/data frames to said receiving location during periods when both voice information and data information are to be transmitted;
(f) during periods when said voice/data frames are received at said receiving location, separating at said receiving location said voice bytes and said data bytes in each said voice/data frame;
(g) pulse code demodulating at said receiving location said voice bytes into an analog voice signal at said first sampling rate during periods when only voice information is received; and (h) pulse code demodulating at said receiving location said voice bytes into an analog voice signal at said second sampling rate during periods when both voice information and data information are received.
(a) pulse code modulating said voice signal at a first sampling rate into a series of voice frames during periods when only voice information is to be transmitted, each said voice frame comprising a plurality of voice bytes;
(b) pulse code modulating said voice signal at a second sampling rate less than said first sampling rate into a series of voice frames during periods when both voice information and data information is to be transmitted, each said voice frame comprising a plurality of voice bytes;
(c) merging one or more data bytes with one or more voice bytes to form a voice/data frame during periods when both voice information and data information are to be transmitted, thereby forming a series of voice/data frames comprising both voice bytes and data bytes;
{d) transmitting said voice frames to a receiving location during periods when voice information only is to be transmitted;
(e) transmitting said voice/data frames to said receiving location during periods when both voice information and data information are to be transmitted;
(f) during periods when said voice/data frames are received at said receiving location, separating at said receiving location said voice bytes and said data bytes in each said voice/data frame;
(g) pulse code demodulating at said receiving location said voice bytes into an analog voice signal at said first sampling rate during periods when only voice information is received; and (h) pulse code demodulating at said receiving location said voice bytes into an analog voice signal at said second sampling rate during periods when both voice information and data information are received.
6. A structure for the transmission of analog information and digital information over a single transmission channel comprising: analog-to-digital converter means capable of operating at a first sampling rate during periods when only analog information is to be transmitted, and at a second sampling rate less than said first sampling rate during periods when both analog in-formation and digital information are to be transmitted, said analog-to-digital converter means having an input means for the reception of analog information and an output means from which is transmitted a digital representation of said analog information, said transmitted digital representation comprising a series of voice words, each said voice word having one or more bits; a first buffer memory for storing one or more voice words; a second buffer memory for storing one or more data words, each said data word comprising one or more bits; means for merging one or more voice words stored in said first bufter memory with one or more data words stored in said second buffer memory during periods when both analog information and digital information are to be trans-mitted; and means for transmitting only voice words during periods when only analog information is to be transmitted and for transmitting said merged voice and data words during periods when both analog information and digital infor-mation are to be transmitted.
7. A structure for the reception of analog information and digital information from a pulse code modulated transmission of a series of words, each such series of words comprising only voice words during periods when only analog information is to be received and comprising merged voice and data words during periods when both analog information and digital information are to be received, each said voice and data words having one or more bits, said structure comprising: means for receiving a series of voice words during periods when only analog information is being transmitted and for receiving a series of merged voice and data words during periods when both analog information and digital information are being transmitted; means for separating merged voice and data words during periods when both analog information and digital information are received; a first buffer memory for storing one or more received voice words corresponding to said analog information; a second buffer memory for storing one or more received data words corresponding to said digital infor-mation; and digital-to-analog converter means for converting said received voice words to an analog signal, said digital-to-analog converter means having an input means for receiving voice words and an output means from which is transmitted said analog information represented by said voice words, said digital-to-analog converter means operating at a first sampling rate during periods when only analog information is received, and at a second sampling rate less than said first sampling rate during periods when both analog in-formation and digital information are received.
8. A structure for the transmission and reception of analog information and digital data comprising: an analog input terminal for receiving analog input signal; an analog-to-digital converter means having an input terminal connected to said analog input terminal and also having an output terminal, for converting said analog input signal to a digital representation thereof, said analog-to-digital converter means being capable of sampling said analog input signal at a first sampling rate during periods when only analog infor-mation is to be transmitted, and at a second sampling rate less than said first sampling rate during periods when both analog information and digital data are to be transmitted; a pulse code modulation output terminal for connection to a transmission channel; means for connecting said output terminal of said analog-to-digital converter means to said pulse code modulation output terminal during periods when only analog information is to be transmitted to said trans-mission channel; a pulse code modulation input terminal for connection to said transmission channel; a digital-to-analog converter means having an input terminal and an output terminal, said digital-to-analog converter means being capable of operating at said first sampling rate during periods when only voice information is to be received and at said second sampling rate during periods when analog information and digital data are to be received from said transmission channel; means for connecting said digital-to-analog converter means input terminal to said pulse code modulation input terminal during periods when only analog information is to be received from said transmission channel; means for storing said digital representation of said analog signal during periods when both analog information and digital data are to be trans-mitted to said transmission channel; means for storing said digital data during periods when both analog information and digital data are to be trans-mitted to said transmission channel; means for selectively outputting said digital representation of said analog signal and said digital data to said pulse code modulation output terminal during periods when both analog infor-mation and digital data are to be transmitted to said transmission channel;
means for separating and for storing the digital representation of analog information and the digital data received at said pulse code modulation input terminal during periods when both analog information and digital data are received from said transmission channel; means for outputting said received digital data during periods when both analog information and digital data are received from said transmission channel; means for applying said digital re-presentation of analog information to said digital-to-analog converter input terminal during periods when both analog information and digital data are received from said transmission channel.
means for separating and for storing the digital representation of analog information and the digital data received at said pulse code modulation input terminal during periods when both analog information and digital data are received from said transmission channel; means for outputting said received digital data during periods when both analog information and digital data are received from said transmission channel; means for applying said digital re-presentation of analog information to said digital-to-analog converter input terminal during periods when both analog information and digital data are received from said transmission channel.
9. Structure as in Claim 8 further comprising: a tone generator con-nected to said analog input terminal for transmitting a queuing signal indi-cative of a change from the mode of transmitting only analog information to the mode of transmitting analog information and digital data simultaneously, or vice-versa; a tone decoder connected to said digital-to-analog converter responsive to said queuing signal for controlling said sampling rate of said digital-to-analog converter and said sampling rate of said analog-to-digital converter.
10. Structure as in Claim 8 further comprising: means for transmitting a digital queuing signal indicative of a change from the mode of transmitting only analog information to the mode of transmitting analog information and digital data simultaneously, or vice-versa; means responsive to said queuing signal for controlling said sampling rate of said digital-to-analog converter and said sampling rate of said analog-to-digital converter.
11. The method of transmitting a voice signal and data information on a single channel of claim 5 wherein said second sampling rate is such that during periods when both voice bytes and data bytes are merged to form a voice/data frame, the total number of bytes in the voice/data frame equals the number of voice bytes in said voice frame during periods when only voice information is transmitted.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/222,702 | 1981-01-05 | ||
| US06/222,702 US4377860A (en) | 1981-01-05 | 1981-01-05 | Bandwidth reduction method and structure for combining voice and data in a PCM channel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1162667A true CA1162667A (en) | 1984-02-21 |
Family
ID=22833331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000388436A Expired CA1162667A (en) | 1981-01-05 | 1981-10-21 | Bandwidth reduction method and structure for combining voice and data in a pcm channel |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4377860A (en) |
| EP (1) | EP0055902B1 (en) |
| JP (1) | JPS57135567A (en) |
| AT (1) | ATE12154T1 (en) |
| CA (1) | CA1162667A (en) |
| DE (1) | DE3169302D1 (en) |
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-
1981
- 1981-01-05 US US06/222,702 patent/US4377860A/en not_active Expired - Lifetime
- 1981-10-21 CA CA000388436A patent/CA1162667A/en not_active Expired
- 1981-12-11 DE DE8181305847T patent/DE3169302D1/en not_active Expired
- 1981-12-11 AT AT81305847T patent/ATE12154T1/en not_active IP Right Cessation
- 1981-12-11 EP EP81305847A patent/EP0055902B1/en not_active Expired
-
1982
- 1982-01-05 JP JP57000128A patent/JPS57135567A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| EP0055902B1 (en) | 1985-03-13 |
| JPH0435941B2 (en) | 1992-06-12 |
| US4377860A (en) | 1983-03-22 |
| DE3169302D1 (en) | 1985-04-18 |
| ATE12154T1 (en) | 1985-03-15 |
| EP0055902A2 (en) | 1982-07-14 |
| JPS57135567A (en) | 1982-08-21 |
| EP0055902A3 (en) | 1982-08-04 |
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