CA1135854A - Programmable read only memory cell - Google Patents
Programmable read only memory cellInfo
- Publication number
- CA1135854A CA1135854A CA000311762A CA311762A CA1135854A CA 1135854 A CA1135854 A CA 1135854A CA 000311762 A CA000311762 A CA 000311762A CA 311762 A CA311762 A CA 311762A CA 1135854 A CA1135854 A CA 1135854A
- Authority
- CA
- Canada
- Prior art keywords
- junction
- layer
- semiconductor
- diode
- diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 64
- 239000004020 conductor Substances 0.000 description 28
- 238000000034 method Methods 0.000 description 16
- 230000008021 deposition Effects 0.000 description 14
- 238000000151 deposition Methods 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 239000000306 component Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 11
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000009740 moulding (composite fabrication) Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000004927 fusion Effects 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000006378 damage Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 229960001866 silicon dioxide Drugs 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 229910000085 borane Inorganic materials 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052729 chemical element Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000007669 thermal treatment Methods 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 241000557769 Iodes Species 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/926—Elongated lead extending axially through another elongated lead
Abstract
ABSTRACT
Programmable read only memory in which the cells comprise a pn-junction diode and an electrically des-tructible programmable element.
The diode is formed by a junction (4) between two regions (2,3) of a thin layer of (polycrystalline) semiconductor material present in an insulating layer covering a semiconductor body. The electrically destructible programmable element is formed by a portion of the thin semiconductor layer.
Application to programmable read only memories.
Fig. 2.
Programmable read only memory in which the cells comprise a pn-junction diode and an electrically des-tructible programmable element.
The diode is formed by a junction (4) between two regions (2,3) of a thin layer of (polycrystalline) semiconductor material present in an insulating layer covering a semiconductor body. The electrically destructible programmable element is formed by a portion of the thin semiconductor layer.
Application to programmable read only memories.
Fig. 2.
Description
- ~3~
.
The present invention relates to a semiconductor device comprising a progran~able read only memory having cells, which each comprise at least one p-_ junction diode and an electrically destructible programmation element. ~-Certain semiconductor devices of the so-called 'lintegrated circuit" type comprise multiple circuits and it is sometimes necessary, during the manufacture oE the device, to reserve the establishment of certain circuits and to be able to manufacture them in a selective manner after the completion of the device in its envelope~ This is the case, for example, with so-called programmable integrated read only memories in which, in order to write information, circuits selected according to a determined program are established or interrupted definitively by means of electric pulses addressed from the exterior.
Other integrated semiconductor arrangements are known also comprising cells of the same type which arrangements are also programmable, for example certain decoding devices, certain devices for handling data groups. `-These devices will also be designated hereinafter by the ; generic term memories. ~`~
A programmation method in which fusible pro-; grammable elements are used consists in establishing first of all at the possible connection points a connection com-prising a wea~ point where a selectively supplied current pulse may produce a fusion to open the considered clrcuit definitively. One of the first disadvantages of program- `
mation of devices by fusion has been the necessity of operations to locally deposit fusible resistance metals, for example nickel chromiumr on an integrated circuit of semiconductor material which otherwise is homogeneous. It has therefore been endeavoured to provide fuses of semi-conductor material, notably of polycrystalline silicon. ~-This is the case, for example, with the fusible connect-ions described in particular in French Patent Specific-ation 2,168,368 which are formed in a polycrystalline silicon layer deposited on a substrate with the interpos-itiOIl of an insulating layer traversed by the connections . . . .
~3S~
.
The present invention relates to a semiconductor device comprising a progran~able read only memory having cells, which each comprise at least one p-_ junction diode and an electrically destructible programmation element. ~-Certain semiconductor devices of the so-called 'lintegrated circuit" type comprise multiple circuits and it is sometimes necessary, during the manufacture oE the device, to reserve the establishment of certain circuits and to be able to manufacture them in a selective manner after the completion of the device in its envelope~ This is the case, for example, with so-called programmable integrated read only memories in which, in order to write information, circuits selected according to a determined program are established or interrupted definitively by means of electric pulses addressed from the exterior.
Other integrated semiconductor arrangements are known also comprising cells of the same type which arrangements are also programmable, for example certain decoding devices, certain devices for handling data groups. `-These devices will also be designated hereinafter by the ; generic term memories. ~`~
A programmation method in which fusible pro-; grammable elements are used consists in establishing first of all at the possible connection points a connection com-prising a wea~ point where a selectively supplied current pulse may produce a fusion to open the considered clrcuit definitively. One of the first disadvantages of program- `
mation of devices by fusion has been the necessity of operations to locally deposit fusible resistance metals, for example nickel chromiumr on an integrated circuit of semiconductor material which otherwise is homogeneous. It has therefore been endeavoured to provide fuses of semi-conductor material, notably of polycrystalline silicon. ~-This is the case, for example, with the fusible connect-ions described in particular in French Patent Specific-ation 2,168,368 which are formed in a polycrystalline silicon layer deposited on a substrate with the interpos-itiOIl of an insulating layer traversed by the connections . . . .
~3S~
2 PE~F 77-569 .
connecting the fuses to the diodes with which they are in series. The diodes, or the more compl:icated components which are in series with the fuses, are integrated in the substrate, but, besides these components, a place has often to be reserved for associated circuits such as decoder circui~s, addressing circuits, reading circuits, amplifier circuits, etc. which cooperate with the memory cells and which occupy a considerable surface area. The area of the slice necessary to accommodate all these ele-ments is considerable and it appears desirable to reduceit and to be able to fur~her ameliorate the integration density of the devices, in particular for memories which usually comprise a very large number o elements.
Moreover, the programmation method by destruc- ~
15 tion of a junction is known which consists in -the selec~- -ive short-circuiting, by an inverse current pulse which is suficiently strong, of a _-n junction diode called pro-grammation diode provided in any possible connection cir-cuit. However, the methods of localising planar junctions used so far for the manufacture of programmation diodes, for example, the manufacture o so-called isolation diodes of memory cell matrices, impose minimum dimensions which -~
it is not possible to reduce to such an extent as to ohtain a value of the current strength to destroy -the junction -;~
which is compatible with the low supply voltages imposed by technology. In this case also it is necessary to reserve beside the memory cells a site for the associated circuits, which necessit~tes considerable surface area.
Of course, in all these cases programmation pulses must ;
not have any action on the circuit elements which are pre-served.
One of the objects of the invention is to amel-iorate -the integration possibilities of devices program mable by means of electrically destructible elements in a slice having a minimum area.
The invention notably has for its object to pro- ~
vide a semiconductor device comprising at least combin- ;
ations of so-called isolation diodes and destructible ele~
~ ?-~ 5~ ::
connecting the fuses to the diodes with which they are in series. The diodes, or the more compl:icated components which are in series with the fuses, are integrated in the substrate, but, besides these components, a place has often to be reserved for associated circuits such as decoder circui~s, addressing circuits, reading circuits, amplifier circuits, etc. which cooperate with the memory cells and which occupy a considerable surface area. The area of the slice necessary to accommodate all these ele-ments is considerable and it appears desirable to reduceit and to be able to fur~her ameliorate the integration density of the devices, in particular for memories which usually comprise a very large number o elements.
Moreover, the programmation method by destruc- ~
15 tion of a junction is known which consists in -the selec~- -ive short-circuiting, by an inverse current pulse which is suficiently strong, of a _-n junction diode called pro-grammation diode provided in any possible connection cir-cuit. However, the methods of localising planar junctions used so far for the manufacture of programmation diodes, for example, the manufacture o so-called isolation diodes of memory cell matrices, impose minimum dimensions which -~
it is not possible to reduce to such an extent as to ohtain a value of the current strength to destroy -the junction -;~
which is compatible with the low supply voltages imposed by technology. In this case also it is necessary to reserve beside the memory cells a site for the associated circuits, which necessit~tes considerable surface area.
Of course, in all these cases programmation pulses must ;
not have any action on the circuit elements which are pre-served.
One of the objects of the invention is to amel-iorate -the integration possibilities of devices program mable by means of electrically destructible elements in a slice having a minimum area.
The invention notably has for its object to pro- ~
vide a semiconductor device comprising at least combin- ;
ations of so-called isolation diodes and destructible ele~
~ ?-~ 5~ ::
3 PHF 77-569 ments~ and presenting a high integration density and a good homogeneity, which elements and d:iodes can be manu-factured by known methods and have a great reliability.
According to the invention, the semiconductor device comprising a programmable read only memory having cells, which each comprise at least one _-_ junction -diode and an electrically destructible programmation ele-ment is characterized in that, the pn-junction of said one diode is formed between two regions of a thin layer of semiconductor matèrial extending on an insulating layer which is present on a semiconductor body. Prefer-a~ly the combination of said pn-junction and said pro-yrammation element is provided in said thin semiconductor layer, said layer being of poly crystalline semiconductor material.
Due to the isolating diodes of the device and the programmation elements being formed in a same thin layer, the circuits constituted by said diodes and ele-ments have a homogeneous structure and occupy a limited 20 volume. Since the thin layer extends on a semiconductor ;
body, same remains entirely available for associated circuits and for any component other than the diodes and the programmation elements.
In particular, in a preferred embodiment, the diodes and the electrically destructible elements which form part thereof are formed in a thin layer of poly-crystalline silicon which itself is formed on an insul- -ating layer covering a ~ody of monocrystalline silicon in which other components may be formed, the insulating 30 layer being traversed, if desired, by connections con- ;
necting the said diodes or the said elements to said com ponents.
The manufacture of such a device uses known techniques of deposition, implantation, diffusion, selec-tive attack with localisation by masking. The program-mation elements are manufactured simultaneously with the diodes without supplementary operations. Moreover, the insulating layer, advantageously of silicon oxide, pro-~ .
~L3Si8~;~
~ PHF 77-569 vides an appreciable thermal isolation between the des- -tructible element and the semiconductor body.
As the case may be, the destruction of the pro-grammation element may open a circuit which was originally closed, or establish a short-circuit in a circuit which was originally open.
In the former case, the zone of one of the two ~ ;
regions of the diode constituting the destructible element is connected directly to a current supply conductor and prevents a preferential fusion point where the break of the circuit is produced under the effect of a pulse of sufficient energy.
In the latter case the programmation element comprising a lateral junction is connected to a current supply conductor to apply an overvoltage which can short-circuit by an avalanch phenomenon of sufficient energy.
It is to be noted that a junction is said to be lateral when it is limited to a surface substantially normal to ~ ~
the plane of the layer of semiconductor material. ~ ;
; For example, a memory constitu-ted by an XY
matrix of memory cells and by associated decoding and addressing circuits is formed from a network of diodes of polycrystalline silicon extending on a silicon oxide layer covering a-body of monocrystalline silicon in which the associated circuits are integrated. The entlre body is available to form there the components of said associ~
ated circuits. The arrangement of diodes and fuses is homogeneous, the fuses being an integral part of regions of the diodes. Besides, the polycrystalline silicon, -preferably doped, presents characteristics of resistivity and fusion temperature suitable for the realisation of fuses.
Preferably the section of the junction of the proyrammation diode is smaller than one tenth of the section of the junction of the isolating diode, which permits to ensure the programmation without risk for the latter.
Thus, a memory constituted by an X-Y matrix of ~;
:
: ";; ~ " , . ~ .
`" 3L~3S~35~
, 5 PHF 77-569 .
memory points cells and associated circuits, is formed by a network of isolating diodes and programmation diodes of polycrystalline silicon on the upper face of a layer of silicon oxide covering a monocrystalline silicon body in which circuit elements of the associated circuits are integrated. The entire surface area of the body is avail-able to provide there the circuit elements of the associ-ated circuits. The arrangement of the diodes including the programmation diodes is homogeneous.
The invention will now be described in greater detail ~ith reference to the accompanying drawing in which Figure 1 is a diagrammatic sectional view of a read-only memory cell according to the invention taken on the line I-I of Figure 2.
Figure 2 is a plan view of the cell shown in Figure ln Flgure 3 is a diagram of a matrix of a pro~
grammed read only memory.
Fig. 4 is a diagrammatic sectional view taken on the line A-B of Fig. 5 of a programmable memory cell having a fuse, and Fig. 5 i5 the plan view thereof. -Fig. 6 is diagrammatic sectional view taken on the line C-D of Fig. 7 of a programmable memory cell having a destructible junction, and Fig. 7 is the plan view thereof.
Fig. 8 is a diagrammatic sectional view taken on the line E-F of Fig. 9 of a programmable memory cell hav-ing a fuse, and Fig. 9 is the plan view thereo~.
Fig. 10 is a diagrammatic sectional view taken on the line G-H of Fig. 11 of a programmable memory cell having a destructible junction, and Fig. 11 is the plan view thereof.
Fig. 12 is a diagrammatic partial sectional view taken on the line K-L of Fig. 13 of a programmable device 35 comprising associated circuits, and fig. 13 is the partial ;
plan view thereof.
Fig. 14 is a diagram of a progra~nable read only memory having a destructible junction.
~/ `
: ~
,,, ~1351~5~ :
Fig. 15 is a diagram of a programmable read only memory having fuses.
It is to be noted that the dimensions in the drawin~s are not to scale and that notably the dimensions in the direction of thickness are exa~gerated so as to make the Figures clearer and that, in the plan views~ the insulating layers are considered to be transparent. A
programmable read-only memory is manufactured on a semi-conductor body lOl-(Figures l and 2) of monocrystalline lO silicon covered by a layer of silicon dioxide 102. The ~ `~
substrate lOl is, for example, of _-type conductivity and it comprises an epitaxial layer of n-type conductivity in which are formed components of associated circuits, such ~-as decoder circuits, addressing circui-ts or amplifier circuits necessary to write or read information content of the memory. Said epitaxial layer and the components ~;
which are integrated in it are not shown.
A thin layer of polycrystalline silicon has been deposited on the insulating layer 102. The thin layer of polycrystalline silicon comprises several islands which are separated from each other and each of which comprises a region 103 of the -type conductivity and a regiGn 104 of the p-type conductivity forming between them a lateral junction 105, the assembly of the two regions 103 and 104 presenting a narrower intermediate portion of smaller width situated between and contiguous with two portions of larger width, the junction 105 being situated in said -narrower portion. Thus the area of the junction which is substantially normal to the plane of the surface of the ~
30 semiconductor body is reduced. ~;
The regions 103 and 104 and their junction 105 are covered by an insulating layer 106 in which windows lO9 and llO are made. Said windows are made on the wider parts of the regions 103 and 104, respectively, and the contacts on the regions 103 and 104 of the diode are made -through the windows lO9 and llO by means of aluminium conductors deposited by evaporation in a vacuum, for example, a column conductor 107 and a line conductor 108.
~3S~
The programmable memory is generally manufac-tured in the form of an XY matrix comprising lines and columns between which the diodes constitute the memory points or cells. Before programmation, each column of the memory is connected to each line by a junction diode, for example, the diodes shown in the diagram of Figure 3 between the column C23 and the lines L2l, L22, L23, L24.
After programmation, certain diodes are deleted and the corresponding connections are interrupted by the fusion of the semiconductor material of its narrow intermediate portion, for example the connections between the column ~ ~ ;
C22 and the line ~23 or between the column C25 and the line L22 of the diagram of Figure 3.
The method of manufacturing a memory of which ;
the cells are in accordance with the example shown dia-grammatically in Figures 1 and 2 may be carried out by means of operations which are conventionally used in the -manufacture of semiconductors.
Starting from a slice of monocrystalline sili-20 con, the associated circuits of the memory with the com- -ponents and the necessary connections are made in said slice. Said circuits are manufactured according to any known method selected with a view to obtaining the best possible performances and as a function of the desired characterlstics, the conditions to be taken into account being on the one hand that the said components and the said connections can be subjected, without damage, to the thermal treatments which are necessitated by the oeprat-ions of forming the diodes of the memory, and on the other ; ~`
hand that the selected method permits of obtaining asurface of the slice having a very good flatness and being suitable to receive in good conditions a deposition of ~ `
insulating material then of polycrystalline silicon.
The slice in which the ne~essary circuits have been made is then covered by an insulating layer of sili-con dioxide Si~2, preferably deposited chemically from the `
vapour phase in a thickness of the order of lOOOA. Said layer may be replaced by a layer of silicon nitride on a ~,,~ ..
~5~35~ ::
, sub-layer of SiO2 deposited chemically from the vapour phase. The deposition of polycrystalline silicon is then carried out in which the diodes of the cells of the mem-ory are formed; the deposition is carried out starting 5 from silane SiH4, to which borane ~2H6 has been added in `
order that the deposited layer be doped with boron, in a reactor at a temperature between 600 and 700C. The ~`
deposited layer is limited to a thickness of 3000 A and ~;
the borane content is adjusted to obtain a boron concen 10 tration of the order of 1 ol7 atoms/cm3. ~-In the case in which the components and/or the connections already made in the slice cannot withstand high temperatures, the insula-ting layer may be obtained by any of the known oxidation methods under pressure and 15 at low temperature and the deposition o polycrystalline `
silicon may be obtained by a method using the plasma gas techniques at temperatures not exceeding 400C.
The diodes are then locali~ed by etching the ~ ;~
silicon layer through an apertured mask of silicon oxide.
The polycrystaIline silicon is etched by means of a mix-ture of hydrofluoric acid, nitric acid and acetic acid or by etching by means of a plasma on the basis of fluoride.
A fresh mask, preferably, if possible, of silicon nitride, is made to localize the regions of the _ conductivity type of the diodes, by implantation of arsenic ions with a zone determining an arsenic concentration of 5.1017 atoms/cm3.
The device is completed by deposition of an ~-insulating layer of silicon dio~ide in which contact win- `
dows are made and by deposition of an aluminium layer -30 succeeded by an etching treatment to define the connection ~;~
conductors.
The programmable memory cell shown in Figs. ~
and 5 is manufactured with a body 1 of which at least a surface layer is of insulating material~ In a thin layer of semiconductor material a first region 2 of a first con-ductivity type and a second xegion 3 of the opposite con-ductivity type are present, said two regions forming a junction 4. The region 3 has a configuration or outline .
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g PHF 77-569 which presents a narrower portion 5 between the junction
According to the invention, the semiconductor device comprising a programmable read only memory having cells, which each comprise at least one _-_ junction -diode and an electrically destructible programmation ele-ment is characterized in that, the pn-junction of said one diode is formed between two regions of a thin layer of semiconductor matèrial extending on an insulating layer which is present on a semiconductor body. Prefer-a~ly the combination of said pn-junction and said pro-yrammation element is provided in said thin semiconductor layer, said layer being of poly crystalline semiconductor material.
Due to the isolating diodes of the device and the programmation elements being formed in a same thin layer, the circuits constituted by said diodes and ele-ments have a homogeneous structure and occupy a limited 20 volume. Since the thin layer extends on a semiconductor ;
body, same remains entirely available for associated circuits and for any component other than the diodes and the programmation elements.
In particular, in a preferred embodiment, the diodes and the electrically destructible elements which form part thereof are formed in a thin layer of poly-crystalline silicon which itself is formed on an insul- -ating layer covering a ~ody of monocrystalline silicon in which other components may be formed, the insulating 30 layer being traversed, if desired, by connections con- ;
necting the said diodes or the said elements to said com ponents.
The manufacture of such a device uses known techniques of deposition, implantation, diffusion, selec-tive attack with localisation by masking. The program-mation elements are manufactured simultaneously with the diodes without supplementary operations. Moreover, the insulating layer, advantageously of silicon oxide, pro-~ .
~L3Si8~;~
~ PHF 77-569 vides an appreciable thermal isolation between the des- -tructible element and the semiconductor body.
As the case may be, the destruction of the pro-grammation element may open a circuit which was originally closed, or establish a short-circuit in a circuit which was originally open.
In the former case, the zone of one of the two ~ ;
regions of the diode constituting the destructible element is connected directly to a current supply conductor and prevents a preferential fusion point where the break of the circuit is produced under the effect of a pulse of sufficient energy.
In the latter case the programmation element comprising a lateral junction is connected to a current supply conductor to apply an overvoltage which can short-circuit by an avalanch phenomenon of sufficient energy.
It is to be noted that a junction is said to be lateral when it is limited to a surface substantially normal to ~ ~
the plane of the layer of semiconductor material. ~ ;
; For example, a memory constitu-ted by an XY
matrix of memory cells and by associated decoding and addressing circuits is formed from a network of diodes of polycrystalline silicon extending on a silicon oxide layer covering a-body of monocrystalline silicon in which the associated circuits are integrated. The entlre body is available to form there the components of said associ~
ated circuits. The arrangement of diodes and fuses is homogeneous, the fuses being an integral part of regions of the diodes. Besides, the polycrystalline silicon, -preferably doped, presents characteristics of resistivity and fusion temperature suitable for the realisation of fuses.
Preferably the section of the junction of the proyrammation diode is smaller than one tenth of the section of the junction of the isolating diode, which permits to ensure the programmation without risk for the latter.
Thus, a memory constituted by an X-Y matrix of ~;
:
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, 5 PHF 77-569 .
memory points cells and associated circuits, is formed by a network of isolating diodes and programmation diodes of polycrystalline silicon on the upper face of a layer of silicon oxide covering a monocrystalline silicon body in which circuit elements of the associated circuits are integrated. The entire surface area of the body is avail-able to provide there the circuit elements of the associ-ated circuits. The arrangement of the diodes including the programmation diodes is homogeneous.
The invention will now be described in greater detail ~ith reference to the accompanying drawing in which Figure 1 is a diagrammatic sectional view of a read-only memory cell according to the invention taken on the line I-I of Figure 2.
Figure 2 is a plan view of the cell shown in Figure ln Flgure 3 is a diagram of a matrix of a pro~
grammed read only memory.
Fig. 4 is a diagrammatic sectional view taken on the line A-B of Fig. 5 of a programmable memory cell having a fuse, and Fig. 5 i5 the plan view thereof. -Fig. 6 is diagrammatic sectional view taken on the line C-D of Fig. 7 of a programmable memory cell having a destructible junction, and Fig. 7 is the plan view thereof.
Fig. 8 is a diagrammatic sectional view taken on the line E-F of Fig. 9 of a programmable memory cell hav-ing a fuse, and Fig. 9 is the plan view thereo~.
Fig. 10 is a diagrammatic sectional view taken on the line G-H of Fig. 11 of a programmable memory cell having a destructible junction, and Fig. 11 is the plan view thereof.
Fig. 12 is a diagrammatic partial sectional view taken on the line K-L of Fig. 13 of a programmable device 35 comprising associated circuits, and fig. 13 is the partial ;
plan view thereof.
Fig. 14 is a diagram of a progra~nable read only memory having a destructible junction.
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: ~
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Fig. 15 is a diagram of a programmable read only memory having fuses.
It is to be noted that the dimensions in the drawin~s are not to scale and that notably the dimensions in the direction of thickness are exa~gerated so as to make the Figures clearer and that, in the plan views~ the insulating layers are considered to be transparent. A
programmable read-only memory is manufactured on a semi-conductor body lOl-(Figures l and 2) of monocrystalline lO silicon covered by a layer of silicon dioxide 102. The ~ `~
substrate lOl is, for example, of _-type conductivity and it comprises an epitaxial layer of n-type conductivity in which are formed components of associated circuits, such ~-as decoder circuits, addressing circui-ts or amplifier circuits necessary to write or read information content of the memory. Said epitaxial layer and the components ~;
which are integrated in it are not shown.
A thin layer of polycrystalline silicon has been deposited on the insulating layer 102. The thin layer of polycrystalline silicon comprises several islands which are separated from each other and each of which comprises a region 103 of the -type conductivity and a regiGn 104 of the p-type conductivity forming between them a lateral junction 105, the assembly of the two regions 103 and 104 presenting a narrower intermediate portion of smaller width situated between and contiguous with two portions of larger width, the junction 105 being situated in said -narrower portion. Thus the area of the junction which is substantially normal to the plane of the surface of the ~
30 semiconductor body is reduced. ~;
The regions 103 and 104 and their junction 105 are covered by an insulating layer 106 in which windows lO9 and llO are made. Said windows are made on the wider parts of the regions 103 and 104, respectively, and the contacts on the regions 103 and 104 of the diode are made -through the windows lO9 and llO by means of aluminium conductors deposited by evaporation in a vacuum, for example, a column conductor 107 and a line conductor 108.
~3S~
The programmable memory is generally manufac-tured in the form of an XY matrix comprising lines and columns between which the diodes constitute the memory points or cells. Before programmation, each column of the memory is connected to each line by a junction diode, for example, the diodes shown in the diagram of Figure 3 between the column C23 and the lines L2l, L22, L23, L24.
After programmation, certain diodes are deleted and the corresponding connections are interrupted by the fusion of the semiconductor material of its narrow intermediate portion, for example the connections between the column ~ ~ ;
C22 and the line ~23 or between the column C25 and the line L22 of the diagram of Figure 3.
The method of manufacturing a memory of which ;
the cells are in accordance with the example shown dia-grammatically in Figures 1 and 2 may be carried out by means of operations which are conventionally used in the -manufacture of semiconductors.
Starting from a slice of monocrystalline sili-20 con, the associated circuits of the memory with the com- -ponents and the necessary connections are made in said slice. Said circuits are manufactured according to any known method selected with a view to obtaining the best possible performances and as a function of the desired characterlstics, the conditions to be taken into account being on the one hand that the said components and the said connections can be subjected, without damage, to the thermal treatments which are necessitated by the oeprat-ions of forming the diodes of the memory, and on the other ; ~`
hand that the selected method permits of obtaining asurface of the slice having a very good flatness and being suitable to receive in good conditions a deposition of ~ `
insulating material then of polycrystalline silicon.
The slice in which the ne~essary circuits have been made is then covered by an insulating layer of sili-con dioxide Si~2, preferably deposited chemically from the `
vapour phase in a thickness of the order of lOOOA. Said layer may be replaced by a layer of silicon nitride on a ~,,~ ..
~5~35~ ::
, sub-layer of SiO2 deposited chemically from the vapour phase. The deposition of polycrystalline silicon is then carried out in which the diodes of the cells of the mem-ory are formed; the deposition is carried out starting 5 from silane SiH4, to which borane ~2H6 has been added in `
order that the deposited layer be doped with boron, in a reactor at a temperature between 600 and 700C. The ~`
deposited layer is limited to a thickness of 3000 A and ~;
the borane content is adjusted to obtain a boron concen 10 tration of the order of 1 ol7 atoms/cm3. ~-In the case in which the components and/or the connections already made in the slice cannot withstand high temperatures, the insula-ting layer may be obtained by any of the known oxidation methods under pressure and 15 at low temperature and the deposition o polycrystalline `
silicon may be obtained by a method using the plasma gas techniques at temperatures not exceeding 400C.
The diodes are then locali~ed by etching the ~ ;~
silicon layer through an apertured mask of silicon oxide.
The polycrystaIline silicon is etched by means of a mix-ture of hydrofluoric acid, nitric acid and acetic acid or by etching by means of a plasma on the basis of fluoride.
A fresh mask, preferably, if possible, of silicon nitride, is made to localize the regions of the _ conductivity type of the diodes, by implantation of arsenic ions with a zone determining an arsenic concentration of 5.1017 atoms/cm3.
The device is completed by deposition of an ~-insulating layer of silicon dio~ide in which contact win- `
dows are made and by deposition of an aluminium layer -30 succeeded by an etching treatment to define the connection ~;~
conductors.
The programmable memory cell shown in Figs. ~
and 5 is manufactured with a body 1 of which at least a surface layer is of insulating material~ In a thin layer of semiconductor material a first region 2 of a first con-ductivity type and a second xegion 3 of the opposite con-ductivity type are present, said two regions forming a junction 4. The region 3 has a configuration or outline .
~? :
~3S~5~ :
g PHF 77-569 which presents a narrower portion 5 between the junction
4 and a contact pad 6. The two regions 2 and 3 and the .
remainder of the surface of the body are covered by an insulating layer 7 having contact apertures 8 for the region 2, and 9 for the region 3. A metal strip 10 is in contact with the region 2 and a metal strip 11 is in con-tact with the region 3. The strip 11 is oriented perpen- ~:
dicularly to the strip 10, lf the programmable memory is of the type having an X-Y matrix, according to the diagram 10 of Fig. 15. Said strip 11 is isolated from the strip 10 ~:
by a second portion of the insulating layer 12; said strip :~
is not shown in the plan view of Fig. 5. : .
The narrow portion 5 of the region 3 of the diode constitutes a weak point and, under a sufficient 15 voltage pulse applied between the conductors 10 and 1]. in ~ ;
the forward direction of the junction 4, a current may cause fusion of said narrow portion 5 and the originally unidirectional circuit is opened definitively. The diode and the fuse constitue a combinati.on which is homogeneous and of minimum dimensions. The manufacture of the diode and the fuse, for example of polycrystalline silicon, with isolation by means of silicon oxide, is obtainèd by tech- :
niques known in semiconductor technology. ~;
The programmable memory cell shown in F.igs. 7 25 and 6 is manufactured with a body 21 of which at least a ::
surface layer is of insulating material and which com-prises, in a thin layer of semiconductor material, a first ~
region 22 of a first conductivity type, a second region 23 :~:
of the opposite conductivity type, said two regions form-ing a junction 24. A third region 25 of the same con~
ductivity type as the region 22 is present and forms with the region 22 a junction 26. The region 23 and the region 25 have a configuration or outline which presents a narrower portion 27 at the area of the junction 26 and the regions 22 and 25 comprise pads for contacting purposes.
The three regions and the remainder of the surface of the body are covered by an insulating layer 28 having contact apertures 29 for the region 22 and 30 for the region 25.
:,' ~', :~
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:
~3~85i~ :
P~IF 77-569 A metal strip 31 is in contact with the region 22 and a metal strip 32 is in contact with the region 25. The metal strip 32 is not shown in the plan view of Fig. 6;
it is oriented perpendicularly to the strip 31 if the memory is of the type having an XY matrix according to the diagram of Fig. 14, and the two strips 31 and 32 are isolated from each other by the insulating layer 33. `
The junction 26 has a small cross-section and ~-under a voltage pulse of sufficient strength applied between the conductors 31 and 32 in the forward direction o~ the junction 24 ~blocking direction of the junction 26~, a current is susceptible of producing the destruction by short-circuit of said junction 26 without damage to the junction 24. The circuit which was originally open due to ~ `
the fact of the two junctions connected in series and in opposition becomes definitively a unidirectional closed circuit. The diode 22, 23 and the diode 23, 25 constitute a combination of elements which is homogeneous and of minimum dimensions. The manufacture of the two diodes, for example of polycrystalline silicon, with isolation by means of silicon oxide, is obtained by techniques known in semiconductor technology.
The programmable memory cell shown in Figs. 8 and 9 is manufactured with a body 71 and comprisesl in a ;
thin layer of polycrystalline silicon, a first region 72 of a first conductivity type and a second region 73 of the opposite conductivity type, said two regions forming a junction of the planar type. The region 72 presents a narrow portion between the said junction and a contact pad 80. The regions 72 and 73 and the remainder of the slice are covered by an insulating layer 74 having contact win~
dows 79 for the region 73 and 77 for the region 72.
metal conductor 75 is in contact with the region 73 ~ia the window 79 and a conductor 76 (which is not shown in 35 FigO 9) oriented perpendicularly to the conductor 75 if ~`;
the memory is o~ the type having an X-Y matri~, is in con~
tact with the region 72 via the window 77. The two con-ductors are isolated from each other by an insulating :' ~3~85~ ~ ~
layer 70. This embodiment of the cell differs from the cell described with reference to Figs. 4 and 5 only as regards the isolating diode which is a planar junction diode instead of being a lateral junction diode. In the two cases a region of the diode presents a narrow portion (78) which constitutes a fusible element. The region 73 is manufactured, for example, by ion implantation. ~ ;
The programmable memory cell shown in Figs. 10 and 11 is manufactured with a substrate 81 and comprises in a thin layer of polycrystalline silicon a first`region 84 of the first conductivity type, a second region 83 of the opposite conductivity type, said two regions forming `~
a planar junction. A third region 82 of the same con-ductivity type as the region 84 forms with the region 83 a lateral junction 89. The regions 82 and 83 have a con-figuration which presents a narrow portion 92 at the area of the junction 89; the regions and the remalnder of the slice are covered by an insulating layer 85 which presents contact windows 88 for the region 82 and 91 for the region 84. A metal conductor 86 is in contact with the region 84 and a metal conductor 87 is in contact with the region 82 (the latter conductor is not shown in Fig. 11) and in the case of an X~Y memory, it is oriented perpendicularly to the conductor 84. The two conductors 87 and 84 are iso-lated from each other by an insulating layer 93.
The cell in this embodiment differs from the ~`
cell described with reference to Figs. 5 and 6 only as `~ ;
regards the isolating diode which is a planar junction diode instead of being a lateral junction diodeO In the two cases, the two regions on either side of the lateral junction form a programmable diode which with a sufficient reverse current is susceptible of short-circuitingO The region 84 is advantageously manufactured by ion implant-ation.
The programmable memory cell shown in Figs. 12 and 13 is of the type having two diodes connected in series and in opposition. The memory is manufactured starting from a substrate 41 of p-type monocrystalline .
~35~
silicon having an epitaxial layer of the _-type in which are formed the components of associated circuits, which cooperated with the cells of the memory, for example, ~`~
decoders and amplifiers necessary to write and read the content of the memory. One of the transistors of the associated circuits is of the npn-type and is shown in the sectional view of Fig. 12; it comprises a collector 42, which is a part of the epitaxial layer and has a buried layer 43 of the n type. Furthermore a base 45 of the p-type has been diffused in the epitaxial layer and an emitter 46 of the n type has been diffused in the base region. The transistor shown is isolated laterally from the other circuit elements by means of areas 47 of silicon oxide reaching the p-type substrate. The surface of the epitaxial layer is covered by a thin insulating layer 48 of silicon oxide which presents apertures for the con~
tacts: an aperture 49 for the contact of the collector pro~ided by a metal conductor 50, an aperture 51 for the contact of the base provided by a metal conductor 52, and `~
an aperture 53 for the contact of the emitter provided by the metal conductor 54. The network of connections of the associated circuits which are integrated in the semi- ;~
conductor body, which network includes the conductors 50, ;
52, 54, is covered by an insulating layer 55 of silicon dioxide, which, if desired, may have apertures at the locations where lines or columns of programmable elements must be connected to an associated circuit.
A thin layer of polycrystalline silicon has been grown on the insulating layer 55 of which portions have been preserved corresponding to the diodes of the memory.
The diodes are similar to those shown in Figs. 6 and 7 and comprise a first n-type region 56, a second n-type region 57 and a third p-type region 58. The junction 59 between the regions 57 and 56 has a larger cross-section than the junction 60 between the regions 58 and 57. Of course a similar memory could be made of cells comprising fusible elements in the form of those shown in Figs. 4 and 5. The junction 60 constitutes the destructible pro-J~3~
grammation element of the memory cell. The programmation pulses are passed through metal conductors 61 contacting the region 56 and through conductors 62 contacting the region 58. The conductor 61 is an aluminium strip deposited by evaporation in a vacuum, and so is the con-ductor 62. The latter contacts the region 58 vla an aperture 63 made in an insulating layer 64 of silicon oxide which covers the whole of the slice and notably the conductors 61.
Several memory cells similar to the cell con-stituted by the regions 56, 57 and 58 are provided on a same line, the contact established via the aperture 63 may serve for two adjacent cells, the region 58 being pro-longed to constitute the third region 65 of a cell adjac-15 ent that described. This arrangement provides a saving in area which may result in an increased integration dens-ity.
The method of manufacturing a memory of which the cells correspond with the example shown diagrammatic-20 ally in Figs. 5 and 6 comprises operations which are con- -ventional techniques used in the manufacture of semicon-ductors.
Starting from a slice of monocrystalline sili-con, the associated circuits of the memory are made in the ~
25 slice, including the circuit elements as well as the nec- ~;
essary connections. Said circuits are manufactured according to any of the known techniques chosen with a view to obtaining the best per~ormances and dependent on the desired characteristics. The conditions which are to be taken into account are on the one hand that said cir-cuit elements and said connections must be able to with-stand without damage the thermal treatments whlch are necessitated by the operations of forming the isolating ~ ~
diodes and the progxammation diodes of the memory, and on ;
35 the other hand that the method chosen should permit to ~-obtain a slice surface which i5 reasonably flat and sus- - ~
ceptible of receiving a deposition of insulating material ~ ;
and then of polycrystalline silicon of sufficient quality.
~. ...
~, ~
., , , , . .. , . . " , . ~ , , : , -: : .
~L~3S~S~ ~
The slice in which the necessary circuits have been made is then covered with an insu:Lating layer of silicon dioxide, preferably deposited chemically from the vapour phase, in a thickness in the order of 1000 A. This layer may be replaced by a layer of silicon nitride on a sublayer of SiO2 deposited chemically from the vapour phase. Then the deposition of polycrystalline silicon is effected in which the diodes of the memory cells are formed subsequently: the deposition is effected from silane SiH4, to which borane B2H6 has been added so that the deposited layer be doped with boron, in a reactor at a temperature between 600 and 700C. The deposition is con-`:
trolled to provide a layer having a thickness of approxi-mately 3000 A and the content of borane is adjusted to -obtain a boron concentration in the order of 1017 atoms/cm3. `
In the case in which the circuit elements and/or the connections already provided in and/or on the slice ~;
cannot withstand high temperatures, the insulating layer may be obtained by any of -the known methods of oxidation under pressure at low temperature, and the deposition of polycrystalline silicon may be obtained by a method using ~
plasma gas techniques and temperatures not exceeding 400C. `
The diodes are then localised by etching the 25 silicon layers by means of a photoetched silicon oxide `;~
mask. The polycrystalline silicon is attached by means of a mixture of hydrofluoric acid, nitric acid and acetic acid or by etching by means of a plasma on the basis of .
fluoride. A fresh mask, preferably i possible of silicon nitride, is provided to localise the regions of the n~
conductivity type of the diodes, by implantation of arsenic ions with a dose determining an arsenic concen~
tration of 5.1017 atoms/cm3.
The device is completed by deposition of an insulating layer of silicon dioxide in which contact win-dows are opened and hy a deposition of aluminium followed by an etching treatment defining the connection conductors.
A memory manufactured as described may admit of :
~, , . -~ 3~35~
programmation currents ensuring the short-circuit. of the desired junctions of the order of 20 mA if the junctions of the programmation diodes have an area of the order of l /um2. For example, thickness of sil:icon layer is abou~
0.3 /um and the width at the narrowest portion where the unctlon is pre:ent is approximately 3/~m.
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.
. ~ .
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.
:
remainder of the surface of the body are covered by an insulating layer 7 having contact apertures 8 for the region 2, and 9 for the region 3. A metal strip 10 is in contact with the region 2 and a metal strip 11 is in con-tact with the region 3. The strip 11 is oriented perpen- ~:
dicularly to the strip 10, lf the programmable memory is of the type having an X-Y matrix, according to the diagram 10 of Fig. 15. Said strip 11 is isolated from the strip 10 ~:
by a second portion of the insulating layer 12; said strip :~
is not shown in the plan view of Fig. 5. : .
The narrow portion 5 of the region 3 of the diode constitutes a weak point and, under a sufficient 15 voltage pulse applied between the conductors 10 and 1]. in ~ ;
the forward direction of the junction 4, a current may cause fusion of said narrow portion 5 and the originally unidirectional circuit is opened definitively. The diode and the fuse constitue a combinati.on which is homogeneous and of minimum dimensions. The manufacture of the diode and the fuse, for example of polycrystalline silicon, with isolation by means of silicon oxide, is obtainèd by tech- :
niques known in semiconductor technology. ~;
The programmable memory cell shown in F.igs. 7 25 and 6 is manufactured with a body 21 of which at least a ::
surface layer is of insulating material and which com-prises, in a thin layer of semiconductor material, a first ~
region 22 of a first conductivity type, a second region 23 :~:
of the opposite conductivity type, said two regions form-ing a junction 24. A third region 25 of the same con~
ductivity type as the region 22 is present and forms with the region 22 a junction 26. The region 23 and the region 25 have a configuration or outline which presents a narrower portion 27 at the area of the junction 26 and the regions 22 and 25 comprise pads for contacting purposes.
The three regions and the remainder of the surface of the body are covered by an insulating layer 28 having contact apertures 29 for the region 22 and 30 for the region 25.
:,' ~', :~
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:
~3~85i~ :
P~IF 77-569 A metal strip 31 is in contact with the region 22 and a metal strip 32 is in contact with the region 25. The metal strip 32 is not shown in the plan view of Fig. 6;
it is oriented perpendicularly to the strip 31 if the memory is of the type having an XY matrix according to the diagram of Fig. 14, and the two strips 31 and 32 are isolated from each other by the insulating layer 33. `
The junction 26 has a small cross-section and ~-under a voltage pulse of sufficient strength applied between the conductors 31 and 32 in the forward direction o~ the junction 24 ~blocking direction of the junction 26~, a current is susceptible of producing the destruction by short-circuit of said junction 26 without damage to the junction 24. The circuit which was originally open due to ~ `
the fact of the two junctions connected in series and in opposition becomes definitively a unidirectional closed circuit. The diode 22, 23 and the diode 23, 25 constitute a combination of elements which is homogeneous and of minimum dimensions. The manufacture of the two diodes, for example of polycrystalline silicon, with isolation by means of silicon oxide, is obtained by techniques known in semiconductor technology.
The programmable memory cell shown in Figs. 8 and 9 is manufactured with a body 71 and comprisesl in a ;
thin layer of polycrystalline silicon, a first region 72 of a first conductivity type and a second region 73 of the opposite conductivity type, said two regions forming a junction of the planar type. The region 72 presents a narrow portion between the said junction and a contact pad 80. The regions 72 and 73 and the remainder of the slice are covered by an insulating layer 74 having contact win~
dows 79 for the region 73 and 77 for the region 72.
metal conductor 75 is in contact with the region 73 ~ia the window 79 and a conductor 76 (which is not shown in 35 FigO 9) oriented perpendicularly to the conductor 75 if ~`;
the memory is o~ the type having an X-Y matri~, is in con~
tact with the region 72 via the window 77. The two con-ductors are isolated from each other by an insulating :' ~3~85~ ~ ~
layer 70. This embodiment of the cell differs from the cell described with reference to Figs. 4 and 5 only as regards the isolating diode which is a planar junction diode instead of being a lateral junction diode. In the two cases a region of the diode presents a narrow portion (78) which constitutes a fusible element. The region 73 is manufactured, for example, by ion implantation. ~ ;
The programmable memory cell shown in Figs. 10 and 11 is manufactured with a substrate 81 and comprises in a thin layer of polycrystalline silicon a first`region 84 of the first conductivity type, a second region 83 of the opposite conductivity type, said two regions forming `~
a planar junction. A third region 82 of the same con-ductivity type as the region 84 forms with the region 83 a lateral junction 89. The regions 82 and 83 have a con-figuration which presents a narrow portion 92 at the area of the junction 89; the regions and the remalnder of the slice are covered by an insulating layer 85 which presents contact windows 88 for the region 82 and 91 for the region 84. A metal conductor 86 is in contact with the region 84 and a metal conductor 87 is in contact with the region 82 (the latter conductor is not shown in Fig. 11) and in the case of an X~Y memory, it is oriented perpendicularly to the conductor 84. The two conductors 87 and 84 are iso-lated from each other by an insulating layer 93.
The cell in this embodiment differs from the ~`
cell described with reference to Figs. 5 and 6 only as `~ ;
regards the isolating diode which is a planar junction diode instead of being a lateral junction diodeO In the two cases, the two regions on either side of the lateral junction form a programmable diode which with a sufficient reverse current is susceptible of short-circuitingO The region 84 is advantageously manufactured by ion implant-ation.
The programmable memory cell shown in Figs. 12 and 13 is of the type having two diodes connected in series and in opposition. The memory is manufactured starting from a substrate 41 of p-type monocrystalline .
~35~
silicon having an epitaxial layer of the _-type in which are formed the components of associated circuits, which cooperated with the cells of the memory, for example, ~`~
decoders and amplifiers necessary to write and read the content of the memory. One of the transistors of the associated circuits is of the npn-type and is shown in the sectional view of Fig. 12; it comprises a collector 42, which is a part of the epitaxial layer and has a buried layer 43 of the n type. Furthermore a base 45 of the p-type has been diffused in the epitaxial layer and an emitter 46 of the n type has been diffused in the base region. The transistor shown is isolated laterally from the other circuit elements by means of areas 47 of silicon oxide reaching the p-type substrate. The surface of the epitaxial layer is covered by a thin insulating layer 48 of silicon oxide which presents apertures for the con~
tacts: an aperture 49 for the contact of the collector pro~ided by a metal conductor 50, an aperture 51 for the contact of the base provided by a metal conductor 52, and `~
an aperture 53 for the contact of the emitter provided by the metal conductor 54. The network of connections of the associated circuits which are integrated in the semi- ;~
conductor body, which network includes the conductors 50, ;
52, 54, is covered by an insulating layer 55 of silicon dioxide, which, if desired, may have apertures at the locations where lines or columns of programmable elements must be connected to an associated circuit.
A thin layer of polycrystalline silicon has been grown on the insulating layer 55 of which portions have been preserved corresponding to the diodes of the memory.
The diodes are similar to those shown in Figs. 6 and 7 and comprise a first n-type region 56, a second n-type region 57 and a third p-type region 58. The junction 59 between the regions 57 and 56 has a larger cross-section than the junction 60 between the regions 58 and 57. Of course a similar memory could be made of cells comprising fusible elements in the form of those shown in Figs. 4 and 5. The junction 60 constitutes the destructible pro-J~3~
grammation element of the memory cell. The programmation pulses are passed through metal conductors 61 contacting the region 56 and through conductors 62 contacting the region 58. The conductor 61 is an aluminium strip deposited by evaporation in a vacuum, and so is the con-ductor 62. The latter contacts the region 58 vla an aperture 63 made in an insulating layer 64 of silicon oxide which covers the whole of the slice and notably the conductors 61.
Several memory cells similar to the cell con-stituted by the regions 56, 57 and 58 are provided on a same line, the contact established via the aperture 63 may serve for two adjacent cells, the region 58 being pro-longed to constitute the third region 65 of a cell adjac-15 ent that described. This arrangement provides a saving in area which may result in an increased integration dens-ity.
The method of manufacturing a memory of which the cells correspond with the example shown diagrammatic-20 ally in Figs. 5 and 6 comprises operations which are con- -ventional techniques used in the manufacture of semicon-ductors.
Starting from a slice of monocrystalline sili-con, the associated circuits of the memory are made in the ~
25 slice, including the circuit elements as well as the nec- ~;
essary connections. Said circuits are manufactured according to any of the known techniques chosen with a view to obtaining the best per~ormances and dependent on the desired characteristics. The conditions which are to be taken into account are on the one hand that said cir-cuit elements and said connections must be able to with-stand without damage the thermal treatments whlch are necessitated by the operations of forming the isolating ~ ~
diodes and the progxammation diodes of the memory, and on ;
35 the other hand that the method chosen should permit to ~-obtain a slice surface which i5 reasonably flat and sus- - ~
ceptible of receiving a deposition of insulating material ~ ;
and then of polycrystalline silicon of sufficient quality.
~. ...
~, ~
., , , , . .. , . . " , . ~ , , : , -: : .
~L~3S~S~ ~
The slice in which the necessary circuits have been made is then covered with an insu:Lating layer of silicon dioxide, preferably deposited chemically from the vapour phase, in a thickness in the order of 1000 A. This layer may be replaced by a layer of silicon nitride on a sublayer of SiO2 deposited chemically from the vapour phase. Then the deposition of polycrystalline silicon is effected in which the diodes of the memory cells are formed subsequently: the deposition is effected from silane SiH4, to which borane B2H6 has been added so that the deposited layer be doped with boron, in a reactor at a temperature between 600 and 700C. The deposition is con-`:
trolled to provide a layer having a thickness of approxi-mately 3000 A and the content of borane is adjusted to -obtain a boron concentration in the order of 1017 atoms/cm3. `
In the case in which the circuit elements and/or the connections already provided in and/or on the slice ~;
cannot withstand high temperatures, the insulating layer may be obtained by any of -the known methods of oxidation under pressure at low temperature, and the deposition of polycrystalline silicon may be obtained by a method using ~
plasma gas techniques and temperatures not exceeding 400C. `
The diodes are then localised by etching the 25 silicon layers by means of a photoetched silicon oxide `;~
mask. The polycrystalline silicon is attached by means of a mixture of hydrofluoric acid, nitric acid and acetic acid or by etching by means of a plasma on the basis of .
fluoride. A fresh mask, preferably i possible of silicon nitride, is provided to localise the regions of the n~
conductivity type of the diodes, by implantation of arsenic ions with a dose determining an arsenic concen~
tration of 5.1017 atoms/cm3.
The device is completed by deposition of an insulating layer of silicon dioxide in which contact win-dows are opened and hy a deposition of aluminium followed by an etching treatment defining the connection conductors.
A memory manufactured as described may admit of :
~, , . -~ 3~35~
programmation currents ensuring the short-circuit. of the desired junctions of the order of 20 mA if the junctions of the programmation diodes have an area of the order of l /um2. For example, thickness of sil:icon layer is abou~
0.3 /um and the width at the narrowest portion where the unctlon is pre:ent is approximately 3/~m.
"~
' ',. ~
.
. ~ .
~;
~ '''' , ~' ~.
.
:
Claims (11)
THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PRO-PERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor device comprising a programmable read-only memory having a plurality of programmable memory cells which each comprise at least one pn-junction diode and an electrically destructible programmation element, which device comprises:
a semiconductor body an insulating layer on said body a thin layer of semiconductor material extend-ing on said insulating layer, characterized in that said at least one pn-junction diode is formed in said thin layer of semiconductor material between two regions of opposite conductivity types.
a semiconductor body an insulating layer on said body a thin layer of semiconductor material extend-ing on said insulating layer, characterized in that said at least one pn-junction diode is formed in said thin layer of semiconductor material between two regions of opposite conductivity types.
2. A semiconductor device as claimed in Claim 1, characterized in that the combination of said pn-junction and said electrically destructible programmation element is provided in said thin semiconductor layer, said layer being of polycrystalline material.
3. A semiconductor device as claimed in Claim 1, characterized in that the electrically destructible element comprises a strip-shaped portion of said semiconductor layer which portion has a narrowing, an intermediate portion of smaller width being situated between and being contiguous with two portions of larger width, the pn-junction of the diode being situated in said intermediate portion of smaller width.
4. A semiconductor device as claimed in Claim 1, 2 or 3, characterized in that two adjacent pn-junction diodes of adjacent memory cells, which diodes each have their pn-junction formed between two regions of said thin semiconduc-tor layer, share a common region of said layer.
5. A semiconductor device as claimed in Claim 1, characterized in that the said programmation element is a fuse connected in series with said pn-junction diode and is constituted by a portion of one of the two regions of the said diode.
6. A semiconductor device as claimed in Claim 1, PHF. 77-569.
characterized in that the said programmation element is a second pn-junction diode susceptible of being short-circuited, said one and said second diode being connected in series and in opposition, said second diode comprising two semiconductor regions which form a pn-junction, a first of said two semiconductor regions sharing a common zone of said thin semiconductor layer with one of the two regions of the first diode.
characterized in that the said programmation element is a second pn-junction diode susceptible of being short-circuited, said one and said second diode being connected in series and in opposition, said second diode comprising two semiconductor regions which form a pn-junction, a first of said two semiconductor regions sharing a common zone of said thin semiconductor layer with one of the two regions of the first diode.
7. A semiconductor device as claimed in Claim 5 or Claim 6, characterized in that the combination of said one pn-junction diode and said programmation element is provided in a portion of said thin semiconductor layer said portion having a cross-section at the location of said pn-junction of said one diode which is of larger area than the smallest cross-section of said portion at the location of said programming element.
8. A semiconductor device as claimed in Claim 5 or 6, characterized in that a first plurality of the said diodes formed by a junction between two regions of said thin layer of semiconductor material are connected in series with fusible elements formed in the said thin layer and a second plurality of said diodes are connected in series with diodes, susceptible of being short-circuited, formed in the said thin layer.
9. A semiconductor device as claimed in Claim 1, characterized in that the device comprises in addition associated circuits to cooperate with the cells of the read only memory, a plurality of circuit elements of said associated circuits being integrated in said semiconductor body.
10. A semiconductor device as claimed in Claim 9, characterized in that said semiconductor body is a mono-crystalline body, said integrated circuit elements being located at least in part below the area of said thin layer which is occupied by the cells of the read only memory.
11. A semiconductor device as claimed in Claim 1, characterized in that the diodes and the destructible programmation elements are formed in a thin layer of poly-crystalline silicon deposited on a layer of silicon oxide covering a semiconductor body of monocrystalline silicon.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7729477A FR2404922A1 (en) | 1977-09-30 | 1977-09-30 | PROM cells with diodes and fuses - has PN junction diode and electrically destructible element to re-form broken junction or open new junction |
| FR7729477 | 1977-09-30 | ||
| FR7810208A FR2422224A1 (en) | 1978-04-06 | 1978-04-06 | PROM cells with diodes and fuses - has PN junction diode and electrically destructible element to re-form broken junction or open new junction |
| FR7810208 | 1978-04-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1135854A true CA1135854A (en) | 1982-11-16 |
Family
ID=26220243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000311762A Expired CA1135854A (en) | 1977-09-30 | 1978-09-21 | Programmable read only memory cell |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4494135A (en) |
| JP (1) | JPS5812742B2 (en) |
| CA (1) | CA1135854A (en) |
| DE (1) | DE2841467C2 (en) |
| GB (1) | GB2005078B (en) |
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| DE1524879A1 (en) * | 1967-11-09 | 1970-11-26 | Ibm Deutschland | Read-only memory for data processing systems |
| US3651385A (en) * | 1968-09-18 | 1972-03-21 | Sony Corp | Semiconductor device including a polycrystalline diode |
| US3582908A (en) * | 1969-03-10 | 1971-06-01 | Bell Telephone Labor Inc | Writing a read-only memory while protecting nonselected elements |
| BE755039A (en) * | 1969-09-15 | 1971-02-01 | Ibm | PERMANENT SEMI-CONDUCTOR MEMORY |
| DE2015480A1 (en) * | 1970-04-01 | 1971-10-21 | Rohde & Schwarz | Method for producing a resistor or diode matrix with permanently stored information |
| US3699403A (en) * | 1970-10-23 | 1972-10-17 | Rca Corp | Fusible semiconductor device including means for reducing the required fusing current |
| BE794202A (en) * | 1972-01-19 | 1973-05-16 | Intel Corp | FUSE LINK FOR INTEGRATED CIRCUIT ON SEMICONDUCTOR SUBSTRATE FOR MEMORIES |
| US4041518A (en) * | 1973-02-24 | 1977-08-09 | Hitachi, Ltd. | MIS semiconductor device and method of manufacturing the same |
| FR2228271B1 (en) * | 1973-05-04 | 1976-11-12 | Honeywell Bull Soc Ind | |
| CH581904A5 (en) * | 1974-08-29 | 1976-11-15 | Centre Electron Horloger | |
| FR2404895A1 (en) * | 1977-09-30 | 1979-04-27 | Radiotechnique Compelec | PROGRAMMABLE MEMORY CELL WITH SEMICONDUCTOR DIODES |
-
1978
- 1978-09-21 CA CA000311762A patent/CA1135854A/en not_active Expired
- 1978-09-23 DE DE2841467A patent/DE2841467C2/en not_active Expired
- 1978-09-27 GB GB7838321A patent/GB2005078B/en not_active Expired
- 1978-09-30 JP JP53119936A patent/JPS5812742B2/en not_active Expired
-
1982
- 1982-09-28 US US06/425,147 patent/US4494135A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5460581A (en) | 1979-05-16 |
| DE2841467C2 (en) | 1984-06-14 |
| DE2841467A1 (en) | 1979-04-12 |
| GB2005078B (en) | 1982-02-17 |
| JPS5812742B2 (en) | 1983-03-10 |
| GB2005078A (en) | 1979-04-11 |
| US4494135A (en) | 1985-01-15 |
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