CA1122329A - Data buffer memory of the "first-in, first-out" type, comprising a variable input and a fixed output - Google Patents
Data buffer memory of the "first-in, first-out" type, comprising a variable input and a fixed outputInfo
- Publication number
- CA1122329A CA1122329A CA317,576A CA317576A CA1122329A CA 1122329 A CA1122329 A CA 1122329A CA 317576 A CA317576 A CA 317576A CA 1122329 A CA1122329 A CA 1122329A
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- buffer
- data
- register
- logic means
- memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- General Physics & Mathematics (AREA)
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- Communication Control (AREA)
- Logic Circuits (AREA)
- Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
Abstract
24.6.1978 ABSTRACT:
A data buffer memory of the first-in, first-out type, comprising an input bus via which data are applied to the buffer, and a fixed output wherefrom data are taken up from the buffer. Per section of the buffer, the buffer comprises logic means whereby a variable input location can be selected. In the logic means status signals are used to determine, in cooperation with signals applied from out-side the buffer, the location where data are to be written in the buffer and, if necessary, when these data in the buf-fer must be shifted to the output.
A data buffer memory of the first-in, first-out type, comprising an input bus via which data are applied to the buffer, and a fixed output wherefrom data are taken up from the buffer. Per section of the buffer, the buffer comprises logic means whereby a variable input location can be selected. In the logic means status signals are used to determine, in cooperation with signals applied from out-side the buffer, the location where data are to be written in the buffer and, if necessary, when these data in the buf-fer must be shifted to the output.
Description
llXZ~2~
P51i~. ~,9X) G~3,~71~J
"l`~ata bu:':`fer mcmc,ry o~ tlle "first-ln, first-out" type, compris:ing a varia70].e i.nr)ut a.nd a ~i~ed 011tpUt.~
Tl-e :invention re:Lates I;o a data bu:f`fer memory of t-he "~irst-ir first~out" type, comprisin~ 1OL~;C meFlns for etlsuring that depending on the fl1.ling of the buffer the i.nput for the data t:o le written is si.tuated substcln--tially as near as possibl~a to the OUtp7~1t :Cor data to b~
reacl, tlllls providing mai1ll.y unin.telrupted contellt~ o~`
the buf`fe~r~ lurtllerlnore comprising an ill}~Ut bus vi.a whi.ch data can be applied to th.e bufrar, notabl.y to an :input of a register thereof assi~;ned for this ~ur-~)oxe, and all output which :is col~Lected to the last re~
gistcr of the buffer alld on which data to be read appec.l-.
wide vari.ety of data buff`er memories o~ s~id "I`i.-st-:in~
first-out" type are ]~nown to ~er~re inter aliA as ~ bu'~er device in digital data prvcessi~lg ~nd commu:llicatlon systems at locations wllere differences occur in t,he rat:c in wllich. input data is supplied and t~Le rate i.:rL whi ch O~ltpUt data is consumed. A number ol` t}le }.no~.73l l>uffer.s is d:ist;i.ng-1ish.ed by simpli.ci..ty of COllStrUCtiOn. nG-tably b)r a pro~ou;lced rLpel;it,i~/e nature of the var...o1ls
P51i~. ~,9X) G~3,~71~J
"l`~ata bu:':`fer mcmc,ry o~ tlle "first-ln, first-out" type, compris:ing a varia70].e i.nr)ut a.nd a ~i~ed 011tpUt.~
Tl-e :invention re:Lates I;o a data bu:f`fer memory of t-he "~irst-ir first~out" type, comprisin~ 1OL~;C meFlns for etlsuring that depending on the fl1.ling of the buffer the i.nput for the data t:o le written is si.tuated substcln--tially as near as possibl~a to the OUtp7~1t :Cor data to b~
reacl, tlllls providing mai1ll.y unin.telrupted contellt~ o~`
the buf`fe~r~ lurtllerlnore comprising an ill}~Ut bus vi.a whi.ch data can be applied to th.e bufrar, notabl.y to an :input of a register thereof assi~;ned for this ~ur-~)oxe, and all output which :is col~Lected to the last re~
gistcr of the buffer alld on which data to be read appec.l-.
wide vari.ety of data buff`er memories o~ s~id "I`i.-st-:in~
first-out" type are ]~nown to ~er~re inter aliA as ~ bu'~er device in digital data prvcessi~lg ~nd commu:llicatlon systems at locations wllere differences occur in t,he rat:c in wllich. input data is supplied and t~Le rate i.:rL whi ch O~ltpUt data is consumed. A number ol` t}le }.no~.73l l>uffer.s is d:ist;i.ng-1ish.ed by simpli.ci..ty of COllStrUCtiOn. nG-tably b)r a pro~ou;lced rLpel;it,i~/e nature of the var...o1ls
2() sect.ions o-f i:hc buf!`er. An cx~mple i.n il-l-i.s re.-,pec~ is formed b~ the bl;-:~er ~e~C`I':ibed -i.ll U~So Pa.t;e~ 745535 (~i5~, 51l;5)-
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problen~ encoull-tered in buf.fers of' this lcind eonsi~its in that, i:E~ the ceapacity of` the b~ffo~- amou:ilts to n seeticlls, a rnessage which .is ap~li.ed to c;n enlpty buffer appea:rs on the OUtpllt o.nl~r a.f-ter n eloek pu].se eyelt-3s. Par-ti.eulaI]y S if rl is 1arge ( ~ 32), :inadmissiblc3 de].ays are then ].iable to oee~r in praetiee. These buI`fers aIe thus eh~.rc~et,e:ri~e~t as hav:ing a fi,.~ed input and a fixed outpu-t.
Also known are bufi`ers ~/h,ieh do not invo.l.ve SUC-II
a. delay beeau.se counting deviees ~:re 1l.sed to en,sure that a variable in~)ut loeation a.s ~el~. as a vari,able output lo-eation of tlle bu:ffer ean be aetivate(l, so that t.he data, notabl.y .in the "empty stat,e", n~ed not; be tra.nspo.r-tc3d thro~lg~
the entire reg:i.ster eaeh tin1e I'or transfc-3r f`rom an input;
to an output. Buf'fer deviees of -tl1i.s kind ~re known f'roln tlle Briti.sh P~te,nt Speeifieation '1473774. ~ ma~jor proble1~ OCCllI`-^
ring in buffer dev:iees of thi.s kind, however, eonsist in tllat the eomplexl~y of eontrol strongly ineIeases, n.ot;ab~
in the case of' buf:~eIs compri~ing a large nunlber oI` sections.
~ounters having a high eoun-..ing eapaeity and ela.bo]-al,e deeo-din~ and s~f3.1,eetion ne-l-;~orlcs for the inputs and outpllts to be as.si,~ned nre requi.red. ~loreo~ r, llnlcirL~ of a large n-urn-ber (>f sn1al] buffers in ord.er te I'or~n a ]al--ger buf:L`cr .is noi;
~oss-iblt wi-1,1lol,lt adciit.ic)lla] eon1r,:1ieatieJls.
~s t-lle need fo:r ci,reu,i.l;s and sys-teil;., wl~ieh arc~ su:it.ab-2~ ~.e fc):L eonsi,rllc-1,.i.c)n in solid-st.ate integratect teehr1i.q-uees.
inereases, tlle i1l-t,ere~t in eonsi.]-1~ct;i.l-g t]-le said b~f':~`er r~e^
. ~ ~
li2Z329 PIIN c~984 21~ . G r 1 ~37cf3 mories sot~at a ~lainly repet:itious cl-aracter is obta:ined strongly gro-~s. Moreover, the cllan~es of link:i.ng a plurali~
ty ef buf'feri ~i.thout incurrin~ addi.-t:i.on.^tl coln~licatiorls are thus generall.y enhancc-~d. A huffer of this kind wh.i.oh.5 moreo~er, does not involve the problel~l o~ lon~ delay tirlles as stated above, is kno-~n froln Unitcd S-ta.tes Paten.t ~peci.fi-cati.o~ 3,6!-~6,526. Thi.s Patent S~eci.fica-tion descri~e3 a buf fer memory of t.he saici typc, comprising a ~-ariable ln~ut and a fi~ed outpu.t, a marher bit indicat:in~-the locati.oll wh.ereto datc mu~st be applied fro~n an :iIlpUi, bu.'i to the buf-fer whi.ch. th~s has a ~ar;.abl.e input. ThiC. locat:i.GIl is a.u empty cell wh.i.ch is si.tllated rlearesl. io the output ol' th.e buffer adjoin.ing a series of filled ce].ls betweerl thts in-. put location alld the output of the buffer. This buf'fer Jnelllo~
ry, howe-ver, has a spec;al construc-tion in which only one marker bit, being a colltro7 bit for the data sectio~. o:t' the buff`er, enables a data path Or 1 bit. Therein, the situai:ior arises in ~h.ich gi~en seetions of thi.s buffer device serve for transportin~ the marker bit as we]] as th.e clata ~it.-;.
'~he risk of the oeeurrenee of errors :;n this buffer, ther~---,ore, is real: if' a 1 bit i.s unc~u].y r~gard.ed as a mal:ke b;.t:, oontrol o.t' the data. fl.ow i5 dis-turbed~ 'r~e risl~. o~
stabi~.ity of t'le bufI`er, theref'ore, i-; no1; imagillaly-, bco.t~lse per~l~tIIe~lt uncertc~inty may a.r:lse ~s reg3.rds ~ e corIec~ in--2rj put ioca.tio.l from the inpui bus to the buffel-.
'~he :in~ellti.on 'has f'or .3.i;s obJect tc, pro~icle a buf' 112Z3~9 P~N ~'3 81i 24~6. 1978 ~`e3~ memory of the described type, somprisi.rJg a variclb1e :in-put and a fixed output, whic}l has a sio1pl.e ancl repet.iti.~e se~ p ancl which, moreover, ofIers IllinilllUln a dc?la~r t~ le of the data and also has a self-^stabilising character. In or-der to achieve thi.C; Gb~ject, the dal,,.t bufl`e3- inemorv is char:ac-teri.z.ed in tlLat said logi.c mean.s arc provided mainl~ per sec~
t:iO11 of the buffer and, ~.~ith thc: e~c~ptic>l1. of l:he conIlec-tions, at least functi.onally seIarately from the sections cf` the buf~er itse.Lf`, th" l.ogic means ~eing of` the type ellabli.n.g the foll.owing sigltals to be gene.rated f`or the bulft?r coln-pr.isi.n~ n rGgi.sters (O,...n-l):
a) app(i.) = crecl~J~0 s (j).s(i-,1), which ind:ica1;es, in react:ion to a request "creq'! frosn outs:icle thc bu:~fer, the register (i) of the buffer in ~hich data are taken up from the in.put ~us, ~ ~ s(j).s(i~1) determiJlillg wl~ere, f.rom a series of ~mpty re~i.sters (O,...i.), the en~.pty register (i) adjoins a subseq~lent filled register ~i-l1);
b) sh(i)=s(l-1).s(i) which, if this conclition is satisi'ied, i.s the shift signal f`or shi.fti~g the data insi.de the ~u~fer :in.t;h.e direction ol' the OUtpllt, s(i--1)--1 indi.ca-tin~ ~he statlls "~u1.l" of` ~l?recedin~ regisl;er and s(i)~ ct-c1icdt.ill~ the statlls "em;>ty" ol th.e rc~le~ t register (i.);
c) ~c;(i) ~ WtliCIl rer~r~?s~ ts t~l~? C' ta(;ll.'~ ~9i~ a.L rOr l.ht? :ri.llilg of a register (1) ;aq~a resul.t of a ~s-.gllaL a~ (J.
~5 oi` sh(:i ) s -t,l-~e signal becco!r~ s(:i):-0 fox 0 ~ -1, .if 112232~
P~ 89811 24 . 6 . 1978 l;he contents of t]:le register (i) are ad~-anced ir-. tbe case of 1;he signa~. ~sh(i~1), tlle status signaL becoming s(.n~ for the register (n-1) if an ack.!lo~ledge sigllal (ers) is gii-en :l`or this pllrpose from ~utsicle th.e burfer after the readlll~ of th.e regisler (n-1).
It is an essential asl~ec-t that there is no mi~-~up of the c~ntrol section formed by t1le lo~i.c me.lns and th~
data trallsport secti.on. The wi~th of the dc?ta pcth of the d.lt~
section call be arbitrari;y chosen. ,.~o restriction e~:i.st_i as regrards the width of the data ~ath. A.s a resul-t of the fact that the register (i) in which data are loaded from the i.n~-put bus is ullarnhiglloucily~ deter~1lincd b~ the first ~mpty regi.s-tcr, taken from the inputS wh.ich is followed by a ful:L re-gister (i.e. thc re~ister preccding the f`irst f`u]l regisker), there never can be uncerta.inty as regards the inp~lt location for the dat~ from the input bus tG Q rsgister of the ~u.~fer.
Instabilit~ is thus precluded. Moreover, a minim~ml delay time through the buffe:r is thus ensured. As a resu]t of the use of the said statuses per sectio3l, bein~ vpdated preferably 20 i.n bistable elements as part .of the logic mean~L.i, a simp].e ~rrange~lent i.5 obta:i.ned wh:ich is .suitable for iil1;egralrion purposeci. As a reslllt of tihe nlodular cilaracte:r oi the COIl s1.:r~c1;i.oll, the reLevallt regiC;ter al?d tlle associ.a1ed l.og~ic mealls ca~l be co11sirllcted as a sol;d-s~te integrated circlli.-t 2~ ~at least pe.r sectior!. of the data bu~rer melllory. I-t is aL.so llZ2~ 9 PirN c~9S~
2~1.6. ,~7c~
po;sible fc~r -the l~ufi'er to consi.sl; oI' ;11; least a g-roup o:r re~i.stels and ai; least a g1~0Up Or ~o"-i.c means per sec(,i.on oi` the bu:EIer, sai.d g].'OllpS being., so~id state inte~ra~ted cir-c~its. S..i,d mc,ciu]a:c constI1lccl;ion a,Lso imp1ies that a plur3~i~
ty of' buf'fer rnemor1es can be read il~r 1.inked i,n order to obtain bur:~er leng~tl~s as deslred.
Ful-tllel~ part: ;.culc 1 s 3.lld cillrlcter:istic3 o:~ tlle buf--f'er merllory wi] J. become app.lrent frolll the :tol1c)~ g des.c3 ip-ti On ol` -~;he embod.iment .
1G The .invelltion will now be descJ ibed by way o.t~ e~:ample witll reference to t.i3e accolllpanyin~ ~lrawingi3. 'l`lle dra-.1:in,~,.s sllow all ~ cample oY ~lembodimenL. whereL.o the i.nventLoll, however, i.s by l]o m~?ans restr:icted.
Fig. 1 SllOWS a circuit diagrlm c,f a "f:rs-t-in, first ou1;" buffer memory comprisin~ a va:ri~b1e input a,3lc1 a :L`ixad output.
Fig . 2 showis 1 b:Lock cli agrarn of an el;lbodil1ler!t Gf' a buf~c`er me~llory in accorcl.lnce wil.ll the inventioll.
which are on the same sheet as Fig. 1, Figs . 3 and l~,/show examp:! es of po~i.bi.l:ities o:l~ par-2(~ titiOl1ill~; l;1le bu:~I`er memvr~ :i n ~iiew o:f,` censtl uct:ion as so1i.{i state :i.nt,egratc-d circu_.ts.
E`ig~. 5 shows arl exa;JJp1e oi' t1le log~.ic mea,ls vr a SC`C-ti,on ~i,) o:f` tl:le b~ f`:Eer meillory.
' 'li`i,g. 6 ShO'l!i'-; all e~.~amL~,Le ,~1' tl-e leg:i.c uleans ol' a sec-~5 t l on ~ G ) o ~ , b ~!:f r~ .-(' Ille l:10 }'-jT ~
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Fig. 7 sho~s an cxample of the logic Ineans of a sectio~l (n-1) of thi? buifer ~lemory.
Fig. 1 sho-~.s a silnpli.L`:i.ecl dia~ra~ of' a "firs-.,-in first~out" b~ff`er Illelnory colnI)r.ising a vaciable inl~ut and a fi~ecd output. Th.e bu.ffer is denotecl by the re~`erence l'il~O.
INB rc~p]esents the input bus vLa clata can be ap1?l.:~cd to thi~ bui'fer, notably to an lnp~t Or an assigned regis-ie-r G--a sectiol~ T(O),...T(n-2), T(l1--1) there(,f. Thi.s constitlltes thi? variable iput ~hich i.s al~o dellotec by a. stroke-cdot ar-row in Fig. 1. The fi~;kcl outpl~t OUT i.s s:i.tuated ai~ th~ out-put of the reg:is-cer o~ ,he last sectj.on T(n--1) of the 1~uf--fi?r memory.
I~i.g. 2 shows the block diagral~l of an en1boc~i~ncn-t of a burfer me111or~Jr in accordance ~iith. the inventic..n. This m~mor-~ co~si.sts of A registeI section comprisi.lli, the regi3-teI~s ~EG(O)...R~G(:i-~1), REG(i)...REG(n-l). rl`hese registers serve for the storage of the appliec7.cliata. ~ach regist~r .P.~G(i.) ~ ay consist of one or more stai~,es 1, 2,...k. Thi.s illu.strate.-i the l~ossi~1ili.ty Of` select:in=or the data ~)a~,h at ra~dorn .-as ~~ar ~ as the ~:iclth is conce:rnecl: 1 bit ciata path reql~iri-s orn~
5ti?.~e ( 1 ) ~el' }~.~G (:i) et.c. In Fii,. 2 the inpu1-. ~us :rN~.~ is sllo~ t,o i,.~t:encl ac.ross the lei-~isters. ~ach rei~is'er ~EG(i.) ~L?.S
it:s il`pUis (of ea i,h ~st aC~;c 1, ?.,...k) c:onilect~;~d l;o tl-~e b~ 3 :L~i)'`. .A~D-i'-irc-t;:ion i~ratos are usc~ for this purl~ose :COI, I02, ..IOk I`or the rc~l.e~3.llt, legrj.ster si,a~,es 1, 2,...k Cf t:he :I:'C?-`~ llZZ329 PHN 89~4 2 ~ , I f-j 7 8 giriter R~G(O); . r~ Ii1, li2,..,lih I'or tLe rel.te~allt regi.ster stages 1, 2,...k of the reg.i~ster Rl~ etc. The choice a9 to wh:icll one of tlle regristers REG(i.~ i.s connected to the bu~s INB is deter~i.lled by the logic means l,M(O`...LM(1-1), hM(i),... J,M(r~ hich are pro~ricJ.ed per sec-tioll of t.lle buf fcr. A signal a~)p(O),..,app(i!,... or app(n-1) i5 grenerated ,n sa:ifl log,ic means ancl i.s applied to sai~ unc~tion gates I01,...IOk,... or Ii1,...Ii.l},... or I(n~1,1),,,,I(ll-'i 9k) .
Thus, the one regri.ste~r ~G(i) of t~le buf:r'e.r wllf~reto data are app~.if?d f'rom the bus INB is selected. l`hf3 register REG(J~
o-~ the last section of tlle buI'fer consti.tutes the OUt~llt, OUT
of the b;lfre~. The conterlts of RI~`G~ e always ~vailable on the o~iltpUt OUT. The siglla] S~I gensrate~ in the buffer i~-- dicatc-s wllether or not valid .tnfor~n3.~ioll is ~?resent on i;h~
out}?ut O~T. Whell thesQ data ~tave been tal~erl up by thc StlC'-roun~1.ings (user), an acl;no~ledge sigrllal "crs't ori.gin.atinj=
~I'Olll outside thf?. buffer serves to :-'`ree the registo~r RE;G(~-1) for storing the subseqtle~it data. ~or :the sh:ifting of t'ne ciatd betwee~ he secl:ions iJI t~f~ bufff_r, co.~.lnectio~is c~re ~rovi.ded 20 be~t~een tlle .st;~ge.ci of the ~arious re~ri3-ters, sa.id con.s:~ect;oJls ex.tendilg across AND-functi.orl gates ~IJ~1, U02~...UOk) and lJil, Ui2,...Uik, etc. bet~cell Qll ootptlt of a. precf*di.n&r rsgis-~-lf-r ~t~ f~ f~.~nf~t nn :i.n.put of a no.it ret7~lste.r st~gr..-. TJ:~.e g.~tes IJ01,...U~k art cl-n.cied. by l~ro~n l:ine~ b~3cau~-! tlle3e gcltes, connef.~tf.~(l t:o the i`irst sectio;lS ~-t e n.ot u:3ed. I:,~ t~le e~ ocl.i--llletlt s~'lown .i~ `ig. 2, thf* i.f?pUt~ re .shown to l~co co~lllninefi pcr 112Z;~
r~ 98~l 2ll.6.~9,~
stage of eac:h rr3g.ister ror t.1-le inp~1t from l;hr-~ bus INB as well as ~or thr3 i.nput. for data sh~ `l.ecl f'urt}].r3r from a pre-cedi.ng register stage~ Shlf'ting i.s ei^.fec-ved ~nder the con trol o:E' the shiI`t signa1s generated in thre logic means L~
sh(i). Finall,y, the asse)1lbly :is c;ontrollecl by a. co1ld:itionecl cloc~ signal (not shown)~ i.e. u11der the condit:ion. that app(i) or sh(i~ ls present.
Subsequently-, the buffer memory consists of' a r,on-trol section compri~s,ing the said :Logic n~car1s L,~I(i) per ~r3C-tion of tho buf'fer. The s:igrals genera-ted in theso lo~ic mear3s are, in addition to the said signa:ls al.~p(l) and sh(i):
the status signals s(i.) which cor1stit11te an i,ndicatio11 a~
regflrd.s the full ("1") or empty ("O") 5 tnte o~ a reglstel-, ~EG(i), or a combinatory form thereof: ~ s(~ hich means that, on the bas:is o the Boolean AND-f'urlction of all re-gisters REG(0) to R~G(i.), the stav~ls signal s(j) ha.s a vaiue ~ero (i.e. s(j).~ This is the defi.nition cf` the conditior.
that al.l ~E~(0)...REG(:i) precr3ding R~G(i-~1) are empty. The indication "empty" means that no vali,d int`ormatiol1 is pre--sent therein. Further particuiars o.~ thr3 lOf~:i.C Ineans and the ,; a~socia-ted signa,l,s wi].l, ~e given wiln refcre1lce to the ~'igs.5,6 an~1'7. Th:is is also al~plj.cal)le to the s:i.gnals 'cflck.", being an achnowlec1ge s:ign~l which i.~ output by tlie ~ufrcr in order,to indicate /h~t d.ata applied ha~-e bc,en ~tOI`ed irl a : 2S re~isve~ `G(i.), "creq", l:~ein;~, a reques-v ~roln out~ide the .
llZZ329 :.'HN ~9~4 2l~L.~ 78 ~uf:~er foI ~toring data in 1;he buff`er, and "SFI'r which indi-~
cates that ~ia areA preseIIt in cLt least one of the registers of the buf-.`er, notably in tl-e last regis-ter RECT(n-1 ? f or this type of buI`fer.
Fi.gs. 3 and 4 sllow a numbe7 of possibilities ~07.`
partition.i.ng i;he buf`f`er melnory in ~iew of cons-tr~lc1;ion in the form ol solid sta-i;e inte~rated circu;.ts. The Jnod~lar character of` the buffer mellJory sho~n :in Fig. 2 enables a va.r.iet~- of solu.t:i.ons: the ref~relloes ~rIo~.~.Yri i.n Fig. 3 ind:icate tll~t in-tegratio~ is possi.ble at least p~r sectio of the buffer: a register ~E~(0) is conlb~ ed in ~Lll ~C to-gether with logi.c mealls LM(0). ~he connecti.on bet~een all the~e sectiorls VIi is formed in ~he reg~rister par-t by the in-put bus INB and the cormections imagined w:ithin the b1ls IN~
in the dra~ing between the stages ot` the successive buf.re7:~
sections in view oI` the s}liftillg ol` data from a precedin2 to a next section. The connections betwee7l the .1.ogic mcans and the further input alld OUtpllt signals are sho~n i.n the form of a si.gnal line bun~le CB :in Fig. ~ .
Fig. 4 similarly sho~rs that integrd.tioil is poss:i~le in integrated circuits per gro1lp llI~ or groups !I~:P~I,...J:fIRl~ Or re~:iste-~- R~`G~ CJ(n-l), or per group HI.L~ o.r ~l`OLlpS ~L}~il ~ L ~!11 0 f I Ogl C 111 edlls Ll~0~,...L~l(n--1). 0~v;ous1y, s 0 l i d s..ate cor.structioll L i` completa b~ er memor:ies i71. an IC i.s 2~ a:lso po~.sibl~. The lill'{illg of any choserL constr~-Lction does -- .
112Z3~9 .T'T~IlN 8~84 21~,6.1?~8 not :i.ml~ose problems, as will be expl.aineLl.tler~inafter with ref'e.rence i,o the cletai.led embodirnents of the logic mea,r,s pe.r section oI' the buffer.
Eig. 5 i.s ll det;ailed repre6entation of an embodi-3 Irlent of the logic means i,M~i.) of a buffer .secti.on (i) for the coJltrol. o.f th.e reg:i.ster REG(i) oJ' this sectivn. In tllis embodiment, the logic lTlsans com~J-ise a f l.ipf.~oi ~i having a sei, inpuJG SI and a re.set inpui, RI and outpui,s Q and Q .
This embodi~nent furthernlo.re compri.ses tl-lree log:ic AND~ .nc--tion ~ates ~-l, E.2 an~ E3. Thc logic n~eQns l~ve a sil~ 1.e COI-I~
st:ructiorl. In other embocliments, other lc-gic eletllerlts such as N~.ND-gates etc. may be readily usecl. Xl; i5 IllCrely impGI.'-tant: that the logic f`unctions to ~e perfor~ned by tlle 3.ogic mea~ls can indeed be realised by these n~eans.
13 The fllnc-tiorls realised in the logic ~nealls LM(i.) a.re such tha-t the signals ~e3i.recl. for the coni;rol of th~3 buf`-: fer are 6en~rated. These signal s are:
a) app(i~: the signal which provide~s the tra.~lsfer of the clata from the illpUt bus, via said gates .[il,~..Iik, -to a regi~-ter REG(i) of thL3 buffe.r. This sigllal aP~(i?
(lo~ic ~-vallle), provLded that 1he cond-it-lc,n creq.
~,-0 s(jj.~s(i-~ is "true" (which l~.eans i,ha1; i1, has i;lle Log:Lc va~ e 1~. In ~NT~-function ga-te E3 it i~ cleter~!~ined ~ ether lllis condit;.o,~ is sl:-t:isfied, llo~.re-~-er, fOJ thi.', plll'pOSe it i.s ~irsi, establishe~ i33 t~Le gat;e E~ wlletheI the expressio -112~3i~9 8~8 21~ 37~
~-, s(J)~ hic~ eans whet}lcx the cond.ition tha-t the re~i.s-ter RE~J(i) and all l~receding regist.ers ( i,.i-ii5 e~.plains the sy~rbol ~ as the Bvolean AND fur.ction symbol) n~-:Lst be ~3mpty i.s sati.sfiot~ he vali.dity of sa.id e~pression creq. ~~ - s ( j ) .s(i~ i.s -cested in E3 on the basis of this iIi.formctt:;.;3n anl-i the in`ornlation ~hether -the ncx-t regis1.er R~G(i+1) is full., denot:ed. b~ t}he status si.~nal s(i-~1) "trl~e"
(-1), and the re.qu.est "creq~ fror,1 outside the buff'eir.
b) sh(i.).-s(i-1).s(i). l'his :is 1;1le s~i.ift si.gnal 10 for shift:ing inside the buf.t'er, nota~ly ~ en dat,a have 'been taken uji Lrom thi output of the 13-lffer~ Tl~.e aim is to con~
stantly enfiule t?lat th~ d~lta are presell-t i.n. the buf`fer in a.
non--interr1lptecl rl-iann.er, viewed fronJ the 01ltpU't. Thi.s :i.s achieved. by n1ol~i.toring the conc1iti.on s(i-1). s(l) 'b~- means of the ~.ND-furlctioIl gate ~.1. This condition is "-l;rue", so i;hLil, the shit`1; s:ignal sh(i! appears, if the reP,ister R~G(i.) i..s enpty (~t~tus s(i)=1) an.d iI' the precediIIg rejl~ris-i,er ~EG(i-1) is full (status .s(i-1)=1).
C) C!n the basis of said for11lation of saici signals, the s1,~tl~s sign,lls of the sections of i;he burie~ are also de-telmined. Under tlle condit:ion r1la* app(:i.) or sh.(l.) LS "t:rue' whl.ch n-eaIls -1, the reg~iste~r R~Ci(i) is fi.lled. The s~atu.s the bi`COlr.eS 5~i.) =-i (].ogicalLy ~Yrit'.eil as s(i)~ uecnlin,,r ~ e~
co1ne.~ lle ~.ignal app(i) or sh~i.) se1;s the f'li.I~r-l.o~
~5 to t~e }1osi t,i.on Q=l ~hicll~;p.. e~e~lts 5(i)--i. Whe.n the reg:ister ~ ~ .
112Z3~9 I~I-IN ~981l 2l~.6.l97~i REG(l) :is e!nl~ti.ed, because the contents thereof are ta3cen over, on the basi.s of the signs~l sil(i+l) ~ia said gates Ui1,...l7.ik, by the subsequer].t register RE~(i+l) which is empty or whi.cl has beco!~e ernpty, sh(i~l) ensures that the flip~lop FFi i.s reset, via its reset i.nput RI, to the pOs.itio.ll Q=0, i.e. Q=1 ~ ~ .
Thus, .s(i)=Q...1, ~.r})i ch means the 5 tatus is s(:i)=0.
In conjunction wi.th the request si,gr~a~ "creq", tlla entire buf`rer is controll.ecl by ~eans of these thre~ si.gnsals app(i) sh(i) and s(i.) generlted in the logic nleans LM(i).
As appears from Fi.g. 5, the loglc me~ms ~ i.) com pri.se a ntlmber o:i' inputs! ~.e. .t'or the si~nal3 s (i~
s ~) (, 1 being ~ ) and the re~lusst s:ignal "creq" or the signals s(i*1) and sh(i+l). The outputs of` LM(i) ser~re f`or the sigrlal~ sh(i), s(i) or ~ s(j) and s(i) and., if so desired, al.so i`or "creq" which i5 conducted ~ia the L~I(i.).
These inputs and outpu-ts are i.dentic.--ll for al]. lo-gic means, includjng LM(0) and LM(n-1), whi.ch means t~at tke contents of' tllesc l.ogi.c means are al~ays the same. The repe-titi~-.ity in the buffer memory is thus enSIlrCd.
In or~ler to illustrs~te this lSpe<`t, li`i.g. 6 .ShO~J.5 3.
detai.~ed di;agrclnl Or -the logic mes~ns L.~(û~ which constitute the ~ t .sect.ior.~ of` the buf`.fer .in conju~ction with the re-~isi.er RE~r(O). T:h.e diagram :is su~stantisLlly identics~l I;o li`:i.g.
5 ~ecauC;-! E10 }?erlorols the same ~unct:ion a.g E1 in Fig. 5, E20 the sc~me .lS ~ and ~3C tl-Le same as h'3 i.. n Fig. 5. 'l'he only .
11~2Z329 PllY ~9~4 24.~.1978 d:~rerence consis ts i.n the ~situatiorl of the signals on the lefc~
hand si.~e of the LM(O) in Fi.gure 6. necause there ale no fur-ther preccdi~g SC(`tionSJ no Sig~.la~ S(j) (Oll. lin~ a) at-d no signal s(i-1) (on line b) is possible. In order to enablc tl~e control to be perfoImed after all a signa]. havlllg t;he ].ogic value "1" .is appl.ied to lnput a (dl1 ~precedin~! empty .~
~ ~ s(j)=1) and a sigllal havil7.~ the logi.c vall~e "O" is ap~
pli.eci to input b (preceding is elllpty s(i-1)=0). The si~nals S(i)=9(0) an~1 sh(i)=sh(O) O~lt}-~Ut from this side to precedillg ~sectiolls ~re not I'urtl1.er use~i. unless sections areA ar~l~angecl in front of this first section upon ex.teilsion of the buffer.
In tha-t casc t~le input~ a and b are n.ormally uscd aga.ill. 'rh.er~
fore extensi.on o~ the burier on this side is not problema--tic . Fig. 7 illue~ trates that the coupling of a buf~er on the other side i.c. the rear of a buf~er. tv b_ arranged in fro~t thereof` is not problerllati.c eit]ler. According to tlle sol1ltio shown in ~?.ig. 6 if desired (like in many data processin~;
system applioatlons) it i.s possible f'or the buffer to 1pro-vide an ackno~.~le~ge s:ignal "cack" i.n order to i.ndi.G~Qtte chat app.1.iecl ~ata have been stored in a :regi.s-ler thQreof. When the buf'fer i.s complete].y filled "~rec3" will no-t be. hOnOIIJ:~Ci, ck 'c-~ so "~]~" wil.l not he gellerate~.l. Thi.s is signal:l.3~ if R'~(O~
is fu1.l ~so l~rhen s(G)~ ?..Ck~' can be s:i.mply gc.rle.ra-ted lr t~1e 10 j G mea1ls LM(G) 1~y mean~ v' an ~-D fUllCt;i Ol' gate l~40 ~ ere~r i.t i.s de'erl1ined ~hei;l1e:r ~he collditlon ~s(O) creq h~s ll~,Z329 Z4 ~r.'l~'7~
bee.n sal;isf:ied. This is because in tile case ol` a request; sig-nal c:rt~q.-1 ne~r data can still be stored as ].ong cas the re-glster R13~(0) rellla:in.s e~ )t~ hich ~leafLs s(O).-1). Vn tlle 'ba-5iS Or cacl~ creq.s(O), stored in a flip*l.op (not shc-~vn), acknowleclgement is t'h.us alwa~rs given outside the buf~er itl orclex to slgnify that d~ta have been take3l over. Wh~n the bu~
t`er is co~np:l.e-tely ~ d, ~o ~urtller da-tc-L can be tak~n over ar).d cack dr.e.s not occur (the relt~E~nt :r1.ipflop is reset)~
so that it :is externall~- known (for exal~ple, by the data pro-ce-;sing system) -t.hQt no new3y applled data ha.ve been ta~en o~r~r b~r tll~ buf'~`er.
Similar -to ths :~oregoing, l~i.g~. 7 sho~!s a detailed d,agralrl of' the logic n1ealls JM~n~ vhic1l constitute, ln con-junction wi.th the register REG(n-1), the la.st sectioIl of 1;he buffr~rr. The dia"~rr~m i.s a.gain sub~tantizlly identical. tc- Fig.
5 because E1(ll-'l) represents E1, E2(rl~1) repre:3ents E2 and E3(n-1~ represents ~3. T1le siglla]s ~t the lelt-hQnd side of the ~ig. 7 fully corre~pond to those ~t t~e left-hclrsd s:;de of Fig. 5. The only dlffer~nce co11sists in the situ-ation of the si.g~nals at thc ri,~rht-hancl side ol'IM(r~
in ~ig. 7. Because there are no subsequen'. sections, a signQl. s(~ 1) = s(n~ is not possible. In order tc) ell<~hle ~ontrol -~o be Ejerfo.r~ned, agal.n a sigrlal ~rl =1 (I.ogic 1~v<.~lu~ c^Lp~ . tG tlli.s i.~ Ot. ~lo~e~-v~r~, o~io~L3ly 2~ no S~ 't Sigilal S1l~ri.) a]?~eca';`S . ~ioWr:~rer, ~ec,-ruse R~G~r;.--1) co.rl-~titut:es tll~ OU'tpllt or the 1~1l:E`Ier itsel:t', tlle si.frnal "ers" i.5 - i6 -.
, PHN 898~.~
, 21L.6~1978 presell-t, representing an ackrlowl~dge signa1. ~Lorn o1lt.si.do the buffer7 to indica-te tllat d~-ta have been rencl ~roin the b1lffe3 (i.e. f'rorn R~G/sl-1). There,t'ore, for L,~(n-1) "ers" ~as ~n efI'ect as if a shif`t has taken ~lace, so that it r~lay be stated.: ers=sh(n~. Output ~igna:l.s ~0~ s(J) and s(n~ and "creq") are no-t fulther utili.~ed. ~Iowever, if exten.sion o~
the buffer is necessary o.r.~ if the bu:r~'er is a:rranged i," front of an othor buffer, sai.d signals can be norrrla:L:I.y used ,Igai and extens:ion. of the buf.fer i.s possibl,e withGut any compli~
eations. An adc1i.tional advantacr~e ccjn~:ists in that the si~na1.
s~n-1) ca~ be u~ed as a sl.g.ll~l SFI ~`or out-si.de the ~ i'f'er to signal l;hat at ].ea~t ol-)e sect:ion has beell f:ill.ed. In ~iew of said shifting mechan:isln, tllis seetion will always be the . ].a~t sect:i.on, so that if s(n-l)=1, this status3 i~s decisive ~}~ the i~format.ion (SF~.). This implies that data are plcsent on the O~T llnes.
As regards th.e simple extens,ion pos~sibiiities o.E' the bu*fer, it; is to be noted that tiis e.~tensior does not ne cessar;ly mea.n, notably i.n the case of use o~ so]id s-tàte, :i.n~
te~rated buffers, th~t a11 signa,l .i.ille.S :slust be eontinuecl (to a lle.~t or ~reeeding buf`fer). Ii; i.s suffici6nt to connect a "creo" ~:i.gnal. i~l1ut to a.rl 5,1?~, signal output arl(l to coll:rlect a s;.g;~al ir;.iout '~e,s!' to ~ signa.~. OUtp1l.t "cack" o.f twc iclen-tical burf'ers to l~e coup1.ed to ~acii o-r,hr,~r. .However in l,slat ~'-'5 c,cl~e~ t,~le clelay time ~l~e:re.lses: per arided a~iditi.onal b-1f`:rer llZ~3Z9 .T?I iN 89 8 11-2LI~6. 197~;
the delay time increa.ses by one Wlit (tne minil-1um clela-y ti.llle thro~ h a bufIer then represents one uni';). Usir~g tlli.s so1u--tion it is pre~iented, however, 1,hat a bufI`er IC must be provi~ed with an excessive numbet~ of input/outp~t terminals.
~s a result o~ the descri.~ed log:icc rlleans, a huffer.
rnemory of th.e fi.rst-in, first-out. type is obtained ~hich coml)ri.ses a variahle i.npul and a fiY.ed ~ui,put an~ w]licll al-ways has a m:irJ.imum delay time for newly applle~l ~ata7 thi~
is becau~e new data are always taken up i II the buffe~ as near .to thc outruc cf th0 burfe- as possi.ble. Tlle descri.bed fllnc-tion of tlle apr~(i) .ciigllal ens1lres tl~at a fi.rst. en1pt,? regi.s-ter (r~h;ch tllerefore has o~ly emptJr rcg;.sters a]lea~ of it-se].f) l~rior to a first full registex (i~1) is filled. IJncer-tainty as rega.rds thc l~c:ation of stora~e of the data i.rom t}le inpllt; hu9 in a register (i) is .not pos. sib.le: t~ere i.s alwa-,ys only one :Locuticn for w.hich a~p(i)=1 i.s ~~ali.d. FurtllerD-ore, the si.~nal sh(i) al~ays ensures that "hole.s" arise i71 the buffer only temporaril.y, wllich msans that empty section.s he-t~een fillecl sections are al~ays fi.ll.e~r This imp].:ies ~h~t, ZO if sor,1a~}lere a stat~ls s~ 1 changes illtO s(i)--O as a rasul.t o~ a . ault, SUC]I a "hole" is fi:L:Le~ .immediatel.y. The da-ta presellt; in tl:,e rele~ant regi..ster .~i) are therl lost (9l~ase~
b~ the slli.f.;ed ciata), ~u'.; no uncer~ain (~c.llclj.tiuIl a:,i.seY. If a sta~us s(~ O hecon~es s~:i=1) svinewllere as a resllLL oi j?.
i`;tult~ i.iua,ior i.~:: Sll.fteCI a~ai:~l.st tile ~ 'St ~ :Ll sec-- 1~ -- llZ~3Z9 I~IN 89~1 21! . 6 . 1973 tion .in the bl.1ffer a.ga:in b~ the shifting mecllanisnl and is subsequently shii`ted to the OUtp11t (in reaction to signal~
"ers") in the l~ormal mallner. ~ secti.on containing invalid informati.on has thus been created, but th.~ iniormation d.is-a;opeals 10wards the output and does not cause permanent un-certai.nty i.n the buffe.r. It ~s thus unambiguou~ly achieve~3.
th.a-t the bu~fer i.s self-stabilisillg. Tl--i.s :is an i1~po~t~nt propc-~rty which is required f`or maIly app:iicatiolls in tlle .fie:l.oJ
of data plocessing and comm1ln cation tecl^~.ique. Finally, -.t i~ to be noted that in v:ie;r of the practical constructi.on oi. th.e buf~er, use is rn~de of, f`or example, so-rermed edge-controlled I`lipfl op~ (for example, Signetic type 71~LS71~) because o~ tlle fact. that the status f:Lipflops l~`~i must be ab].e to read the1nselves. It is alternat.ively po.ssible to utili~.e so--terr.led masterjslave flipf].ops. In that case use mu~t be made o~ at l.cast t-~.o clock pulse si~na~.s (in-stead of one clocl~ pulse signal in the above case). How-ever, t]~e principles o'~ the i~lvention are bv no mean~ modi-fied thcreby an~l realisation is readily possihle by ~se skilled in the art.
~ ~ ;
PHI~ SL
2~ .'i57~
problen~ encoull-tered in buf.fers of' this lcind eonsi~its in that, i:E~ the ceapacity of` the b~ffo~- amou:ilts to n seeticlls, a rnessage which .is ap~li.ed to c;n enlpty buffer appea:rs on the OUtpllt o.nl~r a.f-ter n eloek pu].se eyelt-3s. Par-ti.eulaI]y S if rl is 1arge ( ~ 32), :inadmissiblc3 de].ays are then ].iable to oee~r in praetiee. These buI`fers aIe thus eh~.rc~et,e:ri~e~t as hav:ing a fi,.~ed input and a fixed outpu-t.
Also known are bufi`ers ~/h,ieh do not invo.l.ve SUC-II
a. delay beeau.se counting deviees ~:re 1l.sed to en,sure that a variable in~)ut loeation a.s ~el~. as a vari,able output lo-eation of tlle bu:ffer ean be aetivate(l, so that t.he data, notabl.y .in the "empty stat,e", n~ed not; be tra.nspo.r-tc3d thro~lg~
the entire reg:i.ster eaeh tin1e I'or transfc-3r f`rom an input;
to an output. Buf'fer deviees of -tl1i.s kind ~re known f'roln tlle Briti.sh P~te,nt Speeifieation '1473774. ~ ma~jor proble1~ OCCllI`-^
ring in buffer dev:iees of thi.s kind, however, eonsist in tllat the eomplexl~y of eontrol strongly ineIeases, n.ot;ab~
in the case of' buf:~eIs compri~ing a large nunlber oI` sections.
~ounters having a high eoun-..ing eapaeity and ela.bo]-al,e deeo-din~ and s~f3.1,eetion ne-l-;~orlcs for the inputs and outpllts to be as.si,~ned nre requi.red. ~loreo~ r, llnlcirL~ of a large n-urn-ber (>f sn1al] buffers in ord.er te I'or~n a ]al--ger buf:L`cr .is noi;
~oss-iblt wi-1,1lol,lt adciit.ic)lla] eon1r,:1ieatieJls.
~s t-lle need fo:r ci,reu,i.l;s and sys-teil;., wl~ieh arc~ su:it.ab-2~ ~.e fc):L eonsi,rllc-1,.i.c)n in solid-st.ate integratect teehr1i.q-uees.
inereases, tlle i1l-t,ere~t in eonsi.]-1~ct;i.l-g t]-le said b~f':~`er r~e^
. ~ ~
li2Z329 PIIN c~984 21~ . G r 1 ~37cf3 mories sot~at a ~lainly repet:itious cl-aracter is obta:ined strongly gro-~s. Moreover, the cllan~es of link:i.ng a plurali~
ty ef buf'feri ~i.thout incurrin~ addi.-t:i.on.^tl coln~licatiorls are thus generall.y enhancc-~d. A huffer of this kind wh.i.oh.5 moreo~er, does not involve the problel~l o~ lon~ delay tirlles as stated above, is kno-~n froln Unitcd S-ta.tes Paten.t ~peci.fi-cati.o~ 3,6!-~6,526. Thi.s Patent S~eci.fica-tion descri~e3 a buf fer memory of t.he saici typc, comprising a ~-ariable ln~ut and a fi~ed outpu.t, a marher bit indicat:in~-the locati.oll wh.ereto datc mu~st be applied fro~n an :iIlpUi, bu.'i to the buf-fer whi.ch. th~s has a ~ar;.abl.e input. ThiC. locat:i.GIl is a.u empty cell wh.i.ch is si.tllated rlearesl. io the output ol' th.e buffer adjoin.ing a series of filled ce].ls betweerl thts in-. put location alld the output of the buffer. This buf'fer Jnelllo~
ry, howe-ver, has a spec;al construc-tion in which only one marker bit, being a colltro7 bit for the data sectio~. o:t' the buff`er, enables a data path Or 1 bit. Therein, the situai:ior arises in ~h.ich gi~en seetions of thi.s buffer device serve for transportin~ the marker bit as we]] as th.e clata ~it.-;.
'~he risk of the oeeurrenee of errors :;n this buffer, ther~---,ore, is real: if' a 1 bit i.s unc~u].y r~gard.ed as a mal:ke b;.t:, oontrol o.t' the data. fl.ow i5 dis-turbed~ 'r~e risl~. o~
stabi~.ity of t'le bufI`er, theref'ore, i-; no1; imagillaly-, bco.t~lse per~l~tIIe~lt uncertc~inty may a.r:lse ~s reg3.rds ~ e corIec~ in--2rj put ioca.tio.l from the inpui bus to the buffel-.
'~he :in~ellti.on 'has f'or .3.i;s obJect tc, pro~icle a buf' 112Z3~9 P~N ~'3 81i 24~6. 1978 ~`e3~ memory of the described type, somprisi.rJg a variclb1e :in-put and a fixed output, whic}l has a sio1pl.e ancl repet.iti.~e se~ p ancl which, moreover, ofIers IllinilllUln a dc?la~r t~ le of the data and also has a self-^stabilising character. In or-der to achieve thi.C; Gb~ject, the dal,,.t bufl`e3- inemorv is char:ac-teri.z.ed in tlLat said logi.c mean.s arc provided mainl~ per sec~
t:iO11 of the buffer and, ~.~ith thc: e~c~ptic>l1. of l:he conIlec-tions, at least functi.onally seIarately from the sections cf` the buf~er itse.Lf`, th" l.ogic means ~eing of` the type ellabli.n.g the foll.owing sigltals to be gene.rated f`or the bulft?r coln-pr.isi.n~ n rGgi.sters (O,...n-l):
a) app(i.) = crecl~J~0 s (j).s(i-,1), which ind:ica1;es, in react:ion to a request "creq'! frosn outs:icle thc bu:~fer, the register (i) of the buffer in ~hich data are taken up from the in.put ~us, ~ ~ s(j).s(i~1) determiJlillg wl~ere, f.rom a series of ~mpty re~i.sters (O,...i.), the en~.pty register (i) adjoins a subseq~lent filled register ~i-l1);
b) sh(i)=s(l-1).s(i) which, if this conclition is satisi'ied, i.s the shift signal f`or shi.fti~g the data insi.de the ~u~fer :in.t;h.e direction ol' the OUtpllt, s(i--1)--1 indi.ca-tin~ ~he statlls "~u1.l" of` ~l?recedin~ regisl;er and s(i)~ ct-c1icdt.ill~ the statlls "em;>ty" ol th.e rc~le~ t register (i.);
c) ~c;(i) ~ WtliCIl rer~r~?s~ ts t~l~? C' ta(;ll.'~ ~9i~ a.L rOr l.ht? :ri.llilg of a register (1) ;aq~a resul.t of a ~s-.gllaL a~ (J.
~5 oi` sh(:i ) s -t,l-~e signal becco!r~ s(:i):-0 fox 0 ~ -1, .if 112232~
P~ 89811 24 . 6 . 1978 l;he contents of t]:le register (i) are ad~-anced ir-. tbe case of 1;he signa~. ~sh(i~1), tlle status signaL becoming s(.n~ for the register (n-1) if an ack.!lo~ledge sigllal (ers) is gii-en :l`or this pllrpose from ~utsicle th.e burfer after the readlll~ of th.e regisler (n-1).
It is an essential asl~ec-t that there is no mi~-~up of the c~ntrol section formed by t1le lo~i.c me.lns and th~
data trallsport secti.on. The wi~th of the dc?ta pcth of the d.lt~
section call be arbitrari;y chosen. ,.~o restriction e~:i.st_i as regrards the width of the data ~ath. A.s a resul-t of the fact that the register (i) in which data are loaded from the i.n~-put bus is ullarnhiglloucily~ deter~1lincd b~ the first ~mpty regi.s-tcr, taken from the inputS wh.ich is followed by a ful:L re-gister (i.e. thc re~ister preccding the f`irst f`u]l regisker), there never can be uncerta.inty as regards the inp~lt location for the dat~ from the input bus tG Q rsgister of the ~u.~fer.
Instabilit~ is thus precluded. Moreover, a minim~ml delay time through the buffe:r is thus ensured. As a resu]t of the use of the said statuses per sectio3l, bein~ vpdated preferably 20 i.n bistable elements as part .of the logic mean~L.i, a simp].e ~rrange~lent i.5 obta:i.ned wh:ich is .suitable for iil1;egralrion purposeci. As a reslllt of tihe nlodular cilaracte:r oi the COIl s1.:r~c1;i.oll, the reLevallt regiC;ter al?d tlle associ.a1ed l.og~ic mealls ca~l be co11sirllcted as a sol;d-s~te integrated circlli.-t 2~ ~at least pe.r sectior!. of the data bu~rer melllory. I-t is aL.so llZ2~ 9 PirN c~9S~
2~1.6. ,~7c~
po;sible fc~r -the l~ufi'er to consi.sl; oI' ;11; least a g-roup o:r re~i.stels and ai; least a g1~0Up Or ~o"-i.c means per sec(,i.on oi` the bu:EIer, sai.d g].'OllpS being., so~id state inte~ra~ted cir-c~its. S..i,d mc,ciu]a:c constI1lccl;ion a,Lso imp1ies that a plur3~i~
ty of' buf'fer rnemor1es can be read il~r 1.inked i,n order to obtain bur:~er leng~tl~s as deslred.
Ful-tllel~ part: ;.culc 1 s 3.lld cillrlcter:istic3 o:~ tlle buf--f'er merllory wi] J. become app.lrent frolll the :tol1c)~ g des.c3 ip-ti On ol` -~;he embod.iment .
1G The .invelltion will now be descJ ibed by way o.t~ e~:ample witll reference to t.i3e accolllpanyin~ ~lrawingi3. 'l`lle dra-.1:in,~,.s sllow all ~ cample oY ~lembodimenL. whereL.o the i.nventLoll, however, i.s by l]o m~?ans restr:icted.
Fig. 1 SllOWS a circuit diagrlm c,f a "f:rs-t-in, first ou1;" buffer memory comprisin~ a va:ri~b1e input a,3lc1 a :L`ixad output.
Fig . 2 showis 1 b:Lock cli agrarn of an el;lbodil1ler!t Gf' a buf~c`er me~llory in accorcl.lnce wil.ll the inventioll.
which are on the same sheet as Fig. 1, Figs . 3 and l~,/show examp:! es of po~i.bi.l:ities o:l~ par-2(~ titiOl1ill~; l;1le bu:~I`er memvr~ :i n ~iiew o:f,` censtl uct:ion as so1i.{i state :i.nt,egratc-d circu_.ts.
E`ig~. 5 shows arl exa;JJp1e oi' t1le log~.ic mea,ls vr a SC`C-ti,on ~i,) o:f` tl:le b~ f`:Eer meillory.
' 'li`i,g. 6 ShO'l!i'-; all e~.~amL~,Le ,~1' tl-e leg:i.c uleans ol' a sec-~5 t l on ~ G ) o ~ , b ~!:f r~ .-(' Ille l:10 }'-jT ~
~lZZ3~9 PHN
2ll.6. i j~c~
Fig. 7 sho~s an cxample of the logic Ineans of a sectio~l (n-1) of thi? buifer ~lemory.
Fig. 1 sho-~.s a silnpli.L`:i.ecl dia~ra~ of' a "firs-.,-in first~out" b~ff`er Illelnory colnI)r.ising a vaciable inl~ut and a fi~ecd output. Th.e bu.ffer is denotecl by the re~`erence l'il~O.
INB rc~p]esents the input bus vLa clata can be ap1?l.:~cd to thi~ bui'fer, notably to an lnp~t Or an assigned regis-ie-r G--a sectiol~ T(O),...T(n-2), T(l1--1) there(,f. Thi.s constitlltes thi? variable iput ~hich i.s al~o dellotec by a. stroke-cdot ar-row in Fig. 1. The fi~;kcl outpl~t OUT i.s s:i.tuated ai~ th~ out-put of the reg:is-cer o~ ,he last sectj.on T(n--1) of the 1~uf--fi?r memory.
I~i.g. 2 shows the block diagral~l of an en1boc~i~ncn-t of a burfer me111or~Jr in accordance ~iith. the inventic..n. This m~mor-~ co~si.sts of A registeI section comprisi.lli, the regi3-teI~s ~EG(O)...R~G(:i-~1), REG(i)...REG(n-l). rl`hese registers serve for the storage of the appliec7.cliata. ~ach regist~r .P.~G(i.) ~ ay consist of one or more stai~,es 1, 2,...k. Thi.s illu.strate.-i the l~ossi~1ili.ty Of` select:in=or the data ~)a~,h at ra~dorn .-as ~~ar ~ as the ~:iclth is conce:rnecl: 1 bit ciata path reql~iri-s orn~
5ti?.~e ( 1 ) ~el' }~.~G (:i) et.c. In Fii,. 2 the inpu1-. ~us :rN~.~ is sllo~ t,o i,.~t:encl ac.ross the lei-~isters. ~ach rei~is'er ~EG(i.) ~L?.S
it:s il`pUis (of ea i,h ~st aC~;c 1, ?.,...k) c:onilect~;~d l;o tl-~e b~ 3 :L~i)'`. .A~D-i'-irc-t;:ion i~ratos are usc~ for this purl~ose :COI, I02, ..IOk I`or the rc~l.e~3.llt, legrj.ster si,a~,es 1, 2,...k Cf t:he :I:'C?-`~ llZZ329 PHN 89~4 2 ~ , I f-j 7 8 giriter R~G(O); . r~ Ii1, li2,..,lih I'or tLe rel.te~allt regi.ster stages 1, 2,...k of the reg.i~ster Rl~ etc. The choice a9 to wh:icll one of tlle regristers REG(i.~ i.s connected to the bu~s INB is deter~i.lled by the logic means l,M(O`...LM(1-1), hM(i),... J,M(r~ hich are pro~ricJ.ed per sec-tioll of t.lle buf fcr. A signal a~)p(O),..,app(i!,... or app(n-1) i5 grenerated ,n sa:ifl log,ic means ancl i.s applied to sai~ unc~tion gates I01,...IOk,... or Ii1,...Ii.l},... or I(n~1,1),,,,I(ll-'i 9k) .
Thus, the one regri.ste~r ~G(i) of t~le buf:r'e.r wllf~reto data are app~.if?d f'rom the bus INB is selected. l`hf3 register REG(J~
o-~ the last section of tlle buI'fer consti.tutes the OUt~llt, OUT
of the b;lfre~. The conterlts of RI~`G~ e always ~vailable on the o~iltpUt OUT. The siglla] S~I gensrate~ in the buffer i~-- dicatc-s wllether or not valid .tnfor~n3.~ioll is ~?resent on i;h~
out}?ut O~T. Whell thesQ data ~tave been tal~erl up by thc StlC'-roun~1.ings (user), an acl;no~ledge sigrllal "crs't ori.gin.atinj=
~I'Olll outside thf?. buffer serves to :-'`ree the registo~r RE;G(~-1) for storing the subseqtle~it data. ~or :the sh:ifting of t'ne ciatd betwee~ he secl:ions iJI t~f~ bufff_r, co.~.lnectio~is c~re ~rovi.ded 20 be~t~een tlle .st;~ge.ci of the ~arious re~ri3-ters, sa.id con.s:~ect;oJls ex.tendilg across AND-functi.orl gates ~IJ~1, U02~...UOk) and lJil, Ui2,...Uik, etc. bet~cell Qll ootptlt of a. precf*di.n&r rsgis-~-lf-r ~t~ f~ f~.~nf~t nn :i.n.put of a no.it ret7~lste.r st~gr..-. TJ:~.e g.~tes IJ01,...U~k art cl-n.cied. by l~ro~n l:ine~ b~3cau~-! tlle3e gcltes, connef.~tf.~(l t:o the i`irst sectio;lS ~-t e n.ot u:3ed. I:,~ t~le e~ ocl.i--llletlt s~'lown .i~ `ig. 2, thf* i.f?pUt~ re .shown to l~co co~lllninefi pcr 112Z;~
r~ 98~l 2ll.6.~9,~
stage of eac:h rr3g.ister ror t.1-le inp~1t from l;hr-~ bus INB as well as ~or thr3 i.nput. for data sh~ `l.ecl f'urt}].r3r from a pre-cedi.ng register stage~ Shlf'ting i.s ei^.fec-ved ~nder the con trol o:E' the shiI`t signa1s generated in thre logic means L~
sh(i). Finall,y, the asse)1lbly :is c;ontrollecl by a. co1ld:itionecl cloc~ signal (not shown)~ i.e. u11der the condit:ion. that app(i) or sh(i~ ls present.
Subsequently-, the buffer memory consists of' a r,on-trol section compri~s,ing the said :Logic n~car1s L,~I(i) per ~r3C-tion of tho buf'fer. The s:igrals genera-ted in theso lo~ic mear3s are, in addition to the said signa:ls al.~p(l) and sh(i):
the status signals s(i.) which cor1stit11te an i,ndicatio11 a~
regflrd.s the full ("1") or empty ("O") 5 tnte o~ a reglstel-, ~EG(i), or a combinatory form thereof: ~ s(~ hich means that, on the bas:is o the Boolean AND-f'urlction of all re-gisters REG(0) to R~G(i.), the stav~ls signal s(j) ha.s a vaiue ~ero (i.e. s(j).~ This is the defi.nition cf` the conditior.
that al.l ~E~(0)...REG(:i) precr3ding R~G(i-~1) are empty. The indication "empty" means that no vali,d int`ormatiol1 is pre--sent therein. Further particuiars o.~ thr3 lOf~:i.C Ineans and the ,; a~socia-ted signa,l,s wi].l, ~e given wiln refcre1lce to the ~'igs.5,6 an~1'7. Th:is is also al~plj.cal)le to the s:i.gnals 'cflck.", being an achnowlec1ge s:ign~l which i.~ output by tlie ~ufrcr in order,to indicate /h~t d.ata applied ha~-e bc,en ~tOI`ed irl a : 2S re~isve~ `G(i.), "creq", l:~ein;~, a reques-v ~roln out~ide the .
llZZ329 :.'HN ~9~4 2l~L.~ 78 ~uf:~er foI ~toring data in 1;he buff`er, and "SFI'r which indi-~
cates that ~ia areA preseIIt in cLt least one of the registers of the buf-.`er, notably in tl-e last regis-ter RECT(n-1 ? f or this type of buI`fer.
Fi.gs. 3 and 4 sllow a numbe7 of possibilities ~07.`
partition.i.ng i;he buf`f`er melnory in ~iew of cons-tr~lc1;ion in the form ol solid sta-i;e inte~rated circu;.ts. The Jnod~lar character of` the buffer mellJory sho~n :in Fig. 2 enables a va.r.iet~- of solu.t:i.ons: the ref~relloes ~rIo~.~.Yri i.n Fig. 3 ind:icate tll~t in-tegratio~ is possi.ble at least p~r sectio of the buffer: a register ~E~(0) is conlb~ ed in ~Lll ~C to-gether with logi.c mealls LM(0). ~he connecti.on bet~een all the~e sectiorls VIi is formed in ~he reg~rister par-t by the in-put bus INB and the cormections imagined w:ithin the b1ls IN~
in the dra~ing between the stages ot` the successive buf.re7:~
sections in view oI` the s}liftillg ol` data from a precedin2 to a next section. The connections betwee7l the .1.ogic mcans and the further input alld OUtpllt signals are sho~n i.n the form of a si.gnal line bun~le CB :in Fig. ~ .
Fig. 4 similarly sho~rs that integrd.tioil is poss:i~le in integrated circuits per gro1lp llI~ or groups !I~:P~I,...J:fIRl~ Or re~:iste-~- R~`G~ CJ(n-l), or per group HI.L~ o.r ~l`OLlpS ~L}~il ~ L ~!11 0 f I Ogl C 111 edlls Ll~0~,...L~l(n--1). 0~v;ous1y, s 0 l i d s..ate cor.structioll L i` completa b~ er memor:ies i71. an IC i.s 2~ a:lso po~.sibl~. The lill'{illg of any choserL constr~-Lction does -- .
112Z3~9 .T'T~IlN 8~84 21~,6.1?~8 not :i.ml~ose problems, as will be expl.aineLl.tler~inafter with ref'e.rence i,o the cletai.led embodirnents of the logic mea,r,s pe.r section oI' the buffer.
Eig. 5 i.s ll det;ailed repre6entation of an embodi-3 Irlent of the logic means i,M~i.) of a buffer .secti.on (i) for the coJltrol. o.f th.e reg:i.ster REG(i) oJ' this sectivn. In tllis embodiment, the logic lTlsans com~J-ise a f l.ipf.~oi ~i having a sei, inpuJG SI and a re.set inpui, RI and outpui,s Q and Q .
This embodi~nent furthernlo.re compri.ses tl-lree log:ic AND~ .nc--tion ~ates ~-l, E.2 an~ E3. Thc logic n~eQns l~ve a sil~ 1.e COI-I~
st:ructiorl. In other embocliments, other lc-gic eletllerlts such as N~.ND-gates etc. may be readily usecl. Xl; i5 IllCrely impGI.'-tant: that the logic f`unctions to ~e perfor~ned by tlle 3.ogic mea~ls can indeed be realised by these n~eans.
13 The fllnc-tiorls realised in the logic ~nealls LM(i.) a.re such tha-t the signals ~e3i.recl. for the coni;rol of th~3 buf`-: fer are 6en~rated. These signal s are:
a) app(i~: the signal which provide~s the tra.~lsfer of the clata from the illpUt bus, via said gates .[il,~..Iik, -to a regi~-ter REG(i) of thL3 buffe.r. This sigllal aP~(i?
(lo~ic ~-vallle), provLded that 1he cond-it-lc,n creq.
~,-0 s(jj.~s(i-~ is "true" (which l~.eans i,ha1; i1, has i;lle Log:Lc va~ e 1~. In ~NT~-function ga-te E3 it i~ cleter~!~ined ~ ether lllis condit;.o,~ is sl:-t:isfied, llo~.re-~-er, fOJ thi.', plll'pOSe it i.s ~irsi, establishe~ i33 t~Le gat;e E~ wlletheI the expressio -112~3i~9 8~8 21~ 37~
~-, s(J)~ hic~ eans whet}lcx the cond.ition tha-t the re~i.s-ter RE~J(i) and all l~receding regist.ers ( i,.i-ii5 e~.plains the sy~rbol ~ as the Bvolean AND fur.ction symbol) n~-:Lst be ~3mpty i.s sati.sfiot~ he vali.dity of sa.id e~pression creq. ~~ - s ( j ) .s(i~ i.s -cested in E3 on the basis of this iIi.formctt:;.;3n anl-i the in`ornlation ~hether -the ncx-t regis1.er R~G(i+1) is full., denot:ed. b~ t}he status si.~nal s(i-~1) "trl~e"
(-1), and the re.qu.est "creq~ fror,1 outside the buff'eir.
b) sh(i.).-s(i-1).s(i). l'his :is 1;1le s~i.ift si.gnal 10 for shift:ing inside the buf.t'er, nota~ly ~ en dat,a have 'been taken uji Lrom thi output of the 13-lffer~ Tl~.e aim is to con~
stantly enfiule t?lat th~ d~lta are presell-t i.n. the buf`fer in a.
non--interr1lptecl rl-iann.er, viewed fronJ the 01ltpU't. Thi.s :i.s achieved. by n1ol~i.toring the conc1iti.on s(i-1). s(l) 'b~- means of the ~.ND-furlctioIl gate ~.1. This condition is "-l;rue", so i;hLil, the shit`1; s:ignal sh(i! appears, if the reP,ister R~G(i.) i..s enpty (~t~tus s(i)=1) an.d iI' the precediIIg rejl~ris-i,er ~EG(i-1) is full (status .s(i-1)=1).
C) C!n the basis of said for11lation of saici signals, the s1,~tl~s sign,lls of the sections of i;he burie~ are also de-telmined. Under tlle condit:ion r1la* app(:i.) or sh.(l.) LS "t:rue' whl.ch n-eaIls -1, the reg~iste~r R~Ci(i) is fi.lled. The s~atu.s the bi`COlr.eS 5~i.) =-i (].ogicalLy ~Yrit'.eil as s(i)~ uecnlin,,r ~ e~
co1ne.~ lle ~.ignal app(i) or sh~i.) se1;s the f'li.I~r-l.o~
~5 to t~e }1osi t,i.on Q=l ~hicll~;p.. e~e~lts 5(i)--i. Whe.n the reg:ister ~ ~ .
112Z3~9 I~I-IN ~981l 2l~.6.l97~i REG(l) :is e!nl~ti.ed, because the contents thereof are ta3cen over, on the basi.s of the signs~l sil(i+l) ~ia said gates Ui1,...l7.ik, by the subsequer].t register RE~(i+l) which is empty or whi.cl has beco!~e ernpty, sh(i~l) ensures that the flip~lop FFi i.s reset, via its reset i.nput RI, to the pOs.itio.ll Q=0, i.e. Q=1 ~ ~ .
Thus, .s(i)=Q...1, ~.r})i ch means the 5 tatus is s(:i)=0.
In conjunction wi.th the request si,gr~a~ "creq", tlla entire buf`rer is controll.ecl by ~eans of these thre~ si.gnsals app(i) sh(i) and s(i.) generlted in the logic nleans LM(i).
As appears from Fi.g. 5, the loglc me~ms ~ i.) com pri.se a ntlmber o:i' inputs! ~.e. .t'or the si~nal3 s (i~
s ~) (, 1 being ~ ) and the re~lusst s:ignal "creq" or the signals s(i*1) and sh(i+l). The outputs of` LM(i) ser~re f`or the sigrlal~ sh(i), s(i) or ~ s(j) and s(i) and., if so desired, al.so i`or "creq" which i5 conducted ~ia the L~I(i.).
These inputs and outpu-ts are i.dentic.--ll for al]. lo-gic means, includjng LM(0) and LM(n-1), whi.ch means t~at tke contents of' tllesc l.ogi.c means are al~ays the same. The repe-titi~-.ity in the buffer memory is thus enSIlrCd.
In or~ler to illustrs~te this lSpe<`t, li`i.g. 6 .ShO~J.5 3.
detai.~ed di;agrclnl Or -the logic mes~ns L.~(û~ which constitute the ~ t .sect.ior.~ of` the buf`.fer .in conju~ction with the re-~isi.er RE~r(O). T:h.e diagram :is su~stantisLlly identics~l I;o li`:i.g.
5 ~ecauC;-! E10 }?erlorols the same ~unct:ion a.g E1 in Fig. 5, E20 the sc~me .lS ~ and ~3C tl-Le same as h'3 i.. n Fig. 5. 'l'he only .
11~2Z329 PllY ~9~4 24.~.1978 d:~rerence consis ts i.n the ~situatiorl of the signals on the lefc~
hand si.~e of the LM(O) in Fi.gure 6. necause there ale no fur-ther preccdi~g SC(`tionSJ no Sig~.la~ S(j) (Oll. lin~ a) at-d no signal s(i-1) (on line b) is possible. In order to enablc tl~e control to be perfoImed after all a signa]. havlllg t;he ].ogic value "1" .is appl.ied to lnput a (dl1 ~precedin~! empty .~
~ ~ s(j)=1) and a sigllal havil7.~ the logi.c vall~e "O" is ap~
pli.eci to input b (preceding is elllpty s(i-1)=0). The si~nals S(i)=9(0) an~1 sh(i)=sh(O) O~lt}-~Ut from this side to precedillg ~sectiolls ~re not I'urtl1.er use~i. unless sections areA ar~l~angecl in front of this first section upon ex.teilsion of the buffer.
In tha-t casc t~le input~ a and b are n.ormally uscd aga.ill. 'rh.er~
fore extensi.on o~ the burier on this side is not problema--tic . Fig. 7 illue~ trates that the coupling of a buf~er on the other side i.c. the rear of a buf~er. tv b_ arranged in fro~t thereof` is not problerllati.c eit]ler. According to tlle sol1ltio shown in ~?.ig. 6 if desired (like in many data processin~;
system applioatlons) it i.s possible f'or the buffer to 1pro-vide an ackno~.~le~ge s:ignal "cack" i.n order to i.ndi.G~Qtte chat app.1.iecl ~ata have been stored in a :regi.s-ler thQreof. When the buf'fer i.s complete].y filled "~rec3" will no-t be. hOnOIIJ:~Ci, ck 'c-~ so "~]~" wil.l not he gellerate~.l. Thi.s is signal:l.3~ if R'~(O~
is fu1.l ~so l~rhen s(G)~ ?..Ck~' can be s:i.mply gc.rle.ra-ted lr t~1e 10 j G mea1ls LM(G) 1~y mean~ v' an ~-D fUllCt;i Ol' gate l~40 ~ ere~r i.t i.s de'erl1ined ~hei;l1e:r ~he collditlon ~s(O) creq h~s ll~,Z329 Z4 ~r.'l~'7~
bee.n sal;isf:ied. This is because in tile case ol` a request; sig-nal c:rt~q.-1 ne~r data can still be stored as ].ong cas the re-glster R13~(0) rellla:in.s e~ )t~ hich ~leafLs s(O).-1). Vn tlle 'ba-5iS Or cacl~ creq.s(O), stored in a flip*l.op (not shc-~vn), acknowleclgement is t'h.us alwa~rs given outside the buf~er itl orclex to slgnify that d~ta have been take3l over. Wh~n the bu~
t`er is co~np:l.e-tely ~ d, ~o ~urtller da-tc-L can be tak~n over ar).d cack dr.e.s not occur (the relt~E~nt :r1.ipflop is reset)~
so that it :is externall~- known (for exal~ple, by the data pro-ce-;sing system) -t.hQt no new3y applled data ha.ve been ta~en o~r~r b~r tll~ buf'~`er.
Similar -to ths :~oregoing, l~i.g~. 7 sho~!s a detailed d,agralrl of' the logic n1ealls JM~n~ vhic1l constitute, ln con-junction wi.th the register REG(n-1), the la.st sectioIl of 1;he buffr~rr. The dia"~rr~m i.s a.gain sub~tantizlly identical. tc- Fig.
5 because E1(ll-'l) represents E1, E2(rl~1) repre:3ents E2 and E3(n-1~ represents ~3. T1le siglla]s ~t the lelt-hQnd side of the ~ig. 7 fully corre~pond to those ~t t~e left-hclrsd s:;de of Fig. 5. The only dlffer~nce co11sists in the situ-ation of the si.g~nals at thc ri,~rht-hancl side ol'IM(r~
in ~ig. 7. Because there are no subsequen'. sections, a signQl. s(~ 1) = s(n~ is not possible. In order tc) ell<~hle ~ontrol -~o be Ejerfo.r~ned, agal.n a sigrlal ~rl =1 (I.ogic 1~v<.~lu~ c^Lp~ . tG tlli.s i.~ Ot. ~lo~e~-v~r~, o~io~L3ly 2~ no S~ 't Sigilal S1l~ri.) a]?~eca';`S . ~ioWr:~rer, ~ec,-ruse R~G~r;.--1) co.rl-~titut:es tll~ OU'tpllt or the 1~1l:E`Ier itsel:t', tlle si.frnal "ers" i.5 - i6 -.
, PHN 898~.~
, 21L.6~1978 presell-t, representing an ackrlowl~dge signa1. ~Lorn o1lt.si.do the buffer7 to indica-te tllat d~-ta have been rencl ~roin the b1lffe3 (i.e. f'rorn R~G/sl-1). There,t'ore, for L,~(n-1) "ers" ~as ~n efI'ect as if a shif`t has taken ~lace, so that it r~lay be stated.: ers=sh(n~. Output ~igna:l.s ~0~ s(J) and s(n~ and "creq") are no-t fulther utili.~ed. ~Iowever, if exten.sion o~
the buffer is necessary o.r.~ if the bu:r~'er is a:rranged i," front of an othor buffer, sai.d signals can be norrrla:L:I.y used ,Igai and extens:ion. of the buf.fer i.s possibl,e withGut any compli~
eations. An adc1i.tional advantacr~e ccjn~:ists in that the si~na1.
s~n-1) ca~ be u~ed as a sl.g.ll~l SFI ~`or out-si.de the ~ i'f'er to signal l;hat at ].ea~t ol-)e sect:ion has beell f:ill.ed. In ~iew of said shifting mechan:isln, tllis seetion will always be the . ].a~t sect:i.on, so that if s(n-l)=1, this status3 i~s decisive ~}~ the i~format.ion (SF~.). This implies that data are plcsent on the O~T llnes.
As regards th.e simple extens,ion pos~sibiiities o.E' the bu*fer, it; is to be noted that tiis e.~tensior does not ne cessar;ly mea.n, notably i.n the case of use o~ so]id s-tàte, :i.n~
te~rated buffers, th~t a11 signa,l .i.ille.S :slust be eontinuecl (to a lle.~t or ~reeeding buf`fer). Ii; i.s suffici6nt to connect a "creo" ~:i.gnal. i~l1ut to a.rl 5,1?~, signal output arl(l to coll:rlect a s;.g;~al ir;.iout '~e,s!' to ~ signa.~. OUtp1l.t "cack" o.f twc iclen-tical burf'ers to l~e coup1.ed to ~acii o-r,hr,~r. .However in l,slat ~'-'5 c,cl~e~ t,~le clelay time ~l~e:re.lses: per arided a~iditi.onal b-1f`:rer llZ~3Z9 .T?I iN 89 8 11-2LI~6. 197~;
the delay time increa.ses by one Wlit (tne minil-1um clela-y ti.llle thro~ h a bufIer then represents one uni';). Usir~g tlli.s so1u--tion it is pre~iented, however, 1,hat a bufI`er IC must be provi~ed with an excessive numbet~ of input/outp~t terminals.
~s a result o~ the descri.~ed log:icc rlleans, a huffer.
rnemory of th.e fi.rst-in, first-out. type is obtained ~hich coml)ri.ses a variahle i.npul and a fiY.ed ~ui,put an~ w]licll al-ways has a m:irJ.imum delay time for newly applle~l ~ata7 thi~
is becau~e new data are always taken up i II the buffe~ as near .to thc outruc cf th0 burfe- as possi.ble. Tlle descri.bed fllnc-tion of tlle apr~(i) .ciigllal ens1lres tl~at a fi.rst. en1pt,? regi.s-ter (r~h;ch tllerefore has o~ly emptJr rcg;.sters a]lea~ of it-se].f) l~rior to a first full registex (i~1) is filled. IJncer-tainty as rega.rds thc l~c:ation of stora~e of the data i.rom t}le inpllt; hu9 in a register (i) is .not pos. sib.le: t~ere i.s alwa-,ys only one :Locuticn for w.hich a~p(i)=1 i.s ~~ali.d. FurtllerD-ore, the si.~nal sh(i) al~ays ensures that "hole.s" arise i71 the buffer only temporaril.y, wllich msans that empty section.s he-t~een fillecl sections are al~ays fi.ll.e~r This imp].:ies ~h~t, ZO if sor,1a~}lere a stat~ls s~ 1 changes illtO s(i)--O as a rasul.t o~ a . ault, SUC]I a "hole" is fi:L:Le~ .immediatel.y. The da-ta presellt; in tl:,e rele~ant regi..ster .~i) are therl lost (9l~ase~
b~ the slli.f.;ed ciata), ~u'.; no uncer~ain (~c.llclj.tiuIl a:,i.seY. If a sta~us s(~ O hecon~es s~:i=1) svinewllere as a resllLL oi j?.
i`;tult~ i.iua,ior i.~:: Sll.fteCI a~ai:~l.st tile ~ 'St ~ :Ll sec-- 1~ -- llZ~3Z9 I~IN 89~1 21! . 6 . 1973 tion .in the bl.1ffer a.ga:in b~ the shifting mecllanisnl and is subsequently shii`ted to the OUtp11t (in reaction to signal~
"ers") in the l~ormal mallner. ~ secti.on containing invalid informati.on has thus been created, but th.~ iniormation d.is-a;opeals 10wards the output and does not cause permanent un-certai.nty i.n the buffe.r. It ~s thus unambiguou~ly achieve~3.
th.a-t the bu~fer i.s self-stabilisillg. Tl--i.s :is an i1~po~t~nt propc-~rty which is required f`or maIly app:iicatiolls in tlle .fie:l.oJ
of data plocessing and comm1ln cation tecl^~.ique. Finally, -.t i~ to be noted that in v:ie;r of the practical constructi.on oi. th.e buf~er, use is rn~de of, f`or example, so-rermed edge-controlled I`lipfl op~ (for example, Signetic type 71~LS71~) because o~ tlle fact. that the status f:Lipflops l~`~i must be ab].e to read the1nselves. It is alternat.ively po.ssible to utili~.e so--terr.led masterjslave flipf].ops. In that case use mu~t be made o~ at l.cast t-~.o clock pulse si~na~.s (in-stead of one clocl~ pulse signal in the above case). How-ever, t]~e principles o'~ the i~lvention are bv no mean~ modi-fied thcreby an~l realisation is readily possihle by ~se skilled in the art.
~ ~ ;
Claims (10)
THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PRO-PERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A data buffer memory of the first-in, first-out type, having logic means for ensuring that an input for data to be written is situated substantially as near as possible to an output for data to be read depending on the filling of the buffer, thus providing an uninterrupted content of the buffer, said buffer having a plurality of registers, each register having at least one section, furthermore having an input bus for supplying data to an input of a register of said buffer assigned for this purpose, and an output connected to the last register of the buffer on which data to be read appear, said data buffer comprising:
logic means provided for each section of said buffer, said logic means being at least functionally separate from said sections of said buffer except for connec-tions, said logic means being of the type enabling sig-nals to be generated for a buffer having N registers (0,...
N-l):
first logic means for detecting a condition that a register (I) is empty and that the next register (I"l) is full, plus determining where from the series of empty regis-ters, the empty registers adjoins a subsequent filled register, second logic means for generating a shift signal for shifting the data in said buffer in the direction of the output register, indicating the status full of a preceding register and indicating the status empty of the relevant register (I), PHN. 8984.
third logic means for generating a status signal for the filling of a register (I) as the result of data entering said register, said third logic means also serving to generate a status signal for the last register in said buffer when data is read from said last register.
logic means provided for each section of said buffer, said logic means being at least functionally separate from said sections of said buffer except for connec-tions, said logic means being of the type enabling sig-nals to be generated for a buffer having N registers (0,...
N-l):
first logic means for detecting a condition that a register (I) is empty and that the next register (I"l) is full, plus determining where from the series of empty regis-ters, the empty registers adjoins a subsequent filled register, second logic means for generating a shift signal for shifting the data in said buffer in the direction of the output register, indicating the status full of a preceding register and indicating the status empty of the relevant register (I), PHN. 8984.
third logic means for generating a status signal for the filling of a register (I) as the result of data entering said register, said third logic means also serving to generate a status signal for the last register in said buffer when data is read from said last register.
2. A data buffer memory as claimed in Claim 1 fur-ther comprising:
fourth logic means for generating an acknowledge signal outputed by said buffer to indicate that data supplied to said buffer has been stored in a register (I) of said buffer.
fourth logic means for generating an acknowledge signal outputed by said buffer to indicate that data supplied to said buffer has been stored in a register (I) of said buffer.
3. A data buffer memory as claimed in Claim 2 fur-ther comprising:
further logic means for generating a signal indi-cating that at least the first register of said buffer is empty and is able to receive new data.
further logic means for generating a signal indi-cating that at least the first register of said buffer is empty and is able to receive new data.
4. A data buffer memory as claimed in Claim 1 fur-ther comprising:
logic means for generating a status signal on an output of said buffer indicating that data are present in at least the last register of said buffer.
logic means for generating a status signal on an output of said buffer indicating that data are present in at least the last register of said buffer.
5. A data buffer memory as claimed in Claim 1, 2 or 3 wherein said memory is constructed from solid state inte-grated circuits.
6. A data buffer memory as claimed in Claim 4 wherein said memory is constructed from solid state inte-grated circuits.
7. A data buffer memory as claimed in Claim 1, 2 or 3 wherein said memory is constructed from solid state inte-grated circuits and for each section of said buffer a regis-PHN. 8984.
ter and associated logic means form a solid state integrated circuit.
ter and associated logic means form a solid state integrated circuit.
8. A data buffer memory as claimed in Claim 4 wherein said memory is constructed from solid state inte-grated circuits and for each section of said buffer a register and associated logic means form a solid state integrated circuit.
9. A data buffer memory as claimed in Claim 1, 2 or 3 wherein said memory is constructed from solid state inte-grated circuits and said buffer consists of at least one group of registers and at least one group of logic means for each section of said buffer, said groups being solid state integrated circuits.
10. A data buffer memory as claimed in Claim 4 wherein said memory is constructed from solid state inte-grated circuits and said buffer consists of at least one group of registers and at least one group of logic means for each section of said buffer, said groups being solid state integrated circuits.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL7713707A NL7713707A (en) | 1977-12-12 | 1977-12-12 | INFORMATION BUFFER MEMORY OF THE "FIRST-IN, FIRST-OUT" TYPE WITH VARIABLE INPUT AND FIXED OUTPUT. |
| NL7713707 | 1977-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1122329A true CA1122329A (en) | 1982-04-20 |
Family
ID=19829732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA317,576A Expired CA1122329A (en) | 1977-12-12 | 1978-12-07 | Data buffer memory of the "first-in, first-out" type, comprising a variable input and a fixed output |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US4236225A (en) |
| JP (1) | JPS5920139B2 (en) |
| CA (1) | CA1122329A (en) |
| DE (1) | DE2853239A1 (en) |
| FR (1) | FR2411467A1 (en) |
| GB (1) | GB2009984B (en) |
| IT (1) | IT1101479B (en) |
| NL (1) | NL7713707A (en) |
| SE (2) | SE437581B (en) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57164331A (en) * | 1981-04-02 | 1982-10-08 | Nec Corp | Buffer controller |
| JPS57185492A (en) * | 1981-05-11 | 1982-11-15 | Matsushita Electric Ind Co Ltd | Data latch circuit |
| JPS58220293A (en) * | 1982-06-15 | 1983-12-21 | Nec Corp | Storage device |
| US4510581A (en) * | 1983-02-14 | 1985-04-09 | Prime Computer, Inc. | High speed buffer allocation apparatus |
| US4930102A (en) * | 1983-04-29 | 1990-05-29 | The Regents Of The University Of California | Dynamic activity-creating data-driven computer architecture |
| JPS59226923A (en) * | 1983-05-27 | 1984-12-20 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Bus interface apparatus |
| US4598363A (en) * | 1983-07-07 | 1986-07-01 | At&T Bell Laboratories | Adaptive delayed polling of sensors |
| US4592019A (en) * | 1983-08-31 | 1986-05-27 | At&T Bell Laboratories | Bus oriented LIFO/FIFO memory |
| FR2552916B1 (en) * | 1983-09-29 | 1988-06-10 | Thomas Alain | ASYNCHRONOUS QUEUE WITH STACK OF REGISTERS |
| US5038277A (en) * | 1983-11-07 | 1991-08-06 | Digital Equipment Corporation | Adjustable buffer for data communications in a data processing system |
| AU575351B2 (en) * | 1983-11-07 | 1988-07-28 | Digital Equipment Corporation | Data processing system |
| US4764894A (en) * | 1985-01-16 | 1988-08-16 | Varian Associates, Inc. | Multiple FIFO NMR acquisition system |
| US4833655A (en) * | 1985-06-28 | 1989-05-23 | Wang Laboratories, Inc. | FIFO memory with decreased fall-through delay |
| NL8502023A (en) * | 1985-07-15 | 1987-02-02 | Philips Nv | METHOD FOR SWITCHING TIME LOCKS IN A TDM SIGNAL AND APPARATUS FOR PERFORMING THE METHOD |
| US4672646A (en) * | 1986-09-16 | 1987-06-09 | Hewlett-Packard Company | Direct-injection FIFO shift register |
| US4847812A (en) * | 1986-09-18 | 1989-07-11 | Advanced Micro Devices | FIFO memory device including circuit for generating flag signals |
| US4995005A (en) * | 1986-09-18 | 1991-02-19 | Advanced Micro Devices, Inc. | Memory device which can function as two separate memories or a single memory |
| JPS648732A (en) * | 1987-06-30 | 1989-01-12 | Sharp Kk | Digital serial/parallel converter |
| US5115496A (en) * | 1988-01-26 | 1992-05-19 | Nec Corporation | Queue device capable of quickly transferring a digital signal unit of a word length different from a single word length |
| JP2764908B2 (en) * | 1988-02-04 | 1998-06-11 | 日本電気株式会社 | Cascade buffer circuit |
| JP2576616B2 (en) * | 1988-12-29 | 1997-01-29 | カシオ計算機株式会社 | Processing equipment |
| JPH0391188A (en) * | 1989-09-04 | 1991-04-16 | Matsushita Electric Ind Co Ltd | Fifo memory |
| US5095462A (en) * | 1990-05-25 | 1992-03-10 | Advanced Micro Devices, Inc. | Fifo information storage apparatus including status and logic modules for each cell |
| US5412611A (en) * | 1992-03-17 | 1995-05-02 | Fujitsu, Limited | FIFO memory device capable of writing contiguous data into rows |
| US5513224A (en) * | 1993-09-16 | 1996-04-30 | Codex, Corp. | Fill level indicator for self-timed fifo |
| JP3736855B2 (en) * | 1995-07-10 | 2006-01-18 | ジーリンクス インコーポレイテッド | System including field programmable gate array and intelligent memory |
| JP2001505752A (en) | 1997-08-20 | 2001-04-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Temporary data stream processing buffer memory organization with software management adapted for multiple levels of housekeeping |
| JP4841314B2 (en) * | 2006-05-29 | 2011-12-21 | 川崎マイクロエレクトロニクス株式会社 | Data transfer circuit |
| JP6568560B2 (en) | 2017-09-15 | 2019-08-28 | 株式会社Ｓｕｂａｒｕ | Vehicle travel control device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL6600550A (en) * | 1966-01-15 | 1967-07-17 | ||
| US3646526A (en) * | 1970-03-17 | 1972-02-29 | Us Army | Fifo shift register memory with marker and data bit storage |
| NL7014737A (en) * | 1970-10-08 | 1972-04-11 | ||
| GB1289249A (en) * | 1971-05-05 | 1972-09-13 | ||
| US3781821A (en) * | 1972-06-02 | 1973-12-25 | Ibm | Selective shift register |
| US3942163A (en) * | 1974-06-21 | 1976-03-02 | Burroughs Corporation | CCD stack memory organization |
| US3953838A (en) * | 1974-12-30 | 1976-04-27 | Burroughs Corporation | FIFO Buffer register memory utilizing a one-shot data transfer system |
| JPS5247638A (en) * | 1975-10-15 | 1977-04-15 | Toshiba Corp | Information processing device |
| US4095283A (en) * | 1976-07-02 | 1978-06-13 | International Business Machines Corporation | First in-first out memory array containing special bits for replacement addressing |
-
1977
- 1977-12-12 NL NL7713707A patent/NL7713707A/en not_active Application Discontinuation
-
1978
- 1978-11-30 US US05/965,208 patent/US4236225A/en not_active Expired - Lifetime
- 1978-12-07 IT IT30681/78A patent/IT1101479B/en active
- 1978-12-07 CA CA317,576A patent/CA1122329A/en not_active Expired
- 1978-12-08 GB GB7847707A patent/GB2009984B/en not_active Expired
- 1978-12-09 DE DE19782853239 patent/DE2853239A1/en active Granted
- 1978-12-09 JP JP53152598A patent/JPS5920139B2/en not_active Expired
- 1978-12-11 SE SE7812716A patent/SE437581B/en not_active IP Right Cessation
- 1978-12-11 SE SE7812716D patent/SE7812716L/en not_active Application Discontinuation
- 1978-12-11 FR FR7834812A patent/FR2411467A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| US4236225A (en) | 1980-11-25 |
| GB2009984B (en) | 1982-01-27 |
| JPS5920139B2 (en) | 1984-05-11 |
| FR2411467B1 (en) | 1985-01-18 |
| IT7830681A0 (en) | 1978-12-07 |
| JPS5489439A (en) | 1979-07-16 |
| GB2009984A (en) | 1979-06-20 |
| SE437581B (en) | 1985-03-04 |
| DE2853239C2 (en) | 1989-02-02 |
| FR2411467A1 (en) | 1979-07-06 |
| DE2853239A1 (en) | 1979-06-13 |
| SE7812716L (en) | 1979-06-13 |
| IT1101479B (en) | 1985-09-28 |
| NL7713707A (en) | 1979-06-14 |
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