CA1116533A - Digital circuit for accurately detecting changes in the gray scale of a scanned image - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A digital circuit for detecting changes in the gray scale of scanned images is disclosed. Each line of video information produced by scanning the image is digi-tized. Each digital sample is compared to digital samples delayed a predetermined amount to generate a difference signal which is indicative of a change in the gray scale having a component perpendicular to the direction of scan.
The digitized samples of the video signal are also stored in a memory having a capacity sufficient to store data repre-senting a plurality of scan lines with a typical memory having a capacity for storing digital information repre-senting eight scan lines. Selected digital samples from the stored data are compared to samples of the line being scanned to detect changes in the gray scale having a component parallel to the direction of scan. These changes in the gray scale are combined to generate a signal indicative of the central portion of the change in the gray scale of the image being scanned to drive a printer to generate a line drawing with the position of the lines corresponding to the central portion of the changes in gray scale of the scanned image.

Description

47,229 DIGITAI. CII~CUIT FOR ACCURATEI,Y DETECTING
CHANGES IN THE GRAY SCALE OF A SCANNED IMAGE

ABSTRACT OF THE DISCLOSURE
A digital circuit for detecting changes in the gray scale of scanned images is disclosed. Each line of video information produced by scanning the image is digi-tized. Each digital sample is compared to digital samples delayed a predetermined amount to generate a difference signal which is indicative of a change in the gray scale having a component perpendicular to the direction of scan.
The digitized samples of the video signal are also stored in a memory having a capacity sufficient to store daka repre-senting a plurality of scan lines with a typical memory having a capacity for storing digital information repre-senting eight scan lines. Selected digital samples from the stored data are compared to samples of the line being scanned to detect changes iII the gray scale having a component parallel to the direction of scan. These changes in the gray scale are combined to generate a signal indicative of the central portion of the change in the gray scale of the ` image being scanned to drive a printer to generate a line drawing with the position of the llnes corresponding to thecentral portion of the changes in gray scale of the scanned image.
BACKGROUND OF THE IN~ENTION

Field of the Invention:
The invention relates to scannqrs and more parti-cularly to digital scanners for detecting changes in the gray scale of a scanned image to generate a line drawing with the position of the lines corresponding to the central portion of the changes in the gray scale of the scanned image.
Description of the Prior Art:
Typical prior art systems for scanning an image to generate a line drawing with the po,sition of the lines corresponding to the changes in the gray scale o~ a scanned image have relied on analog techni~ues. Changes in the gray scale were generally detected by -taking either the first or second derivative o~ the video signal ~rom the scanner used to scan the image, or some combination o~ these, to generate signals indicative of the changes in gray scale of the scanned image. These systems had limîted capabllity of detect-ing changes in the gray scale which were parallel to the direction of scan. Additionally the line width of the line drawing generated by these systems tended to vary depending on the direction of the line with respect to the direction o~
scannlngO The true edges of out-of-~ocus objects were usually displaced because of the gradual cha~ges in the gray scale resulting from such edges.
~
The system disclosed by this application is all digital and is capable of detecting changes in the gray scale with the detection capability being substantially independent of the direction of the changes in gray s~ale with respect to the scanning. Circuitry is also included which permits the detection o~ the center of gradual changes in the gray scale o~ the image being scanned~ (Slightly out-of-focus photographs of edges o~ objects are an example . . .

47,229 o~ such an image.) This results in a system which is cap-able of producing line drawings with the position of the lines comprising the drawing corresponding to the center of changes in the gray scale with tne capability of detection of changes in the gray scale and controlling the width of the line being substantially independent of direction. This ;~ superior result is produced by detecting changes in the gray scale in a airection parallel to the scanning and ak right angles thereto to generate two signals~ one indicative of changes in the gray scale in a direction perpendicular to scan and a second si~nal indicative of changes in the gray scale parallel to the direction of scanning. Thse two signals are then combined to produce a line drawing on a printer with the lines having an ad~ustable width with the ability to detect changes in gray scale being substantially independent of direction. This :improved result is accom-plished by scanning the image to produce a video signal comprising a plurality of lines. The amplitude of this signal is indicative of the gray scale of the portion of the image being scanned. Each line of this signal ls period-ically sampled to produce digital numbers indicative of the amplitude of this signal at the sample time.
Changes in the gray scale of the scanned lmage in a direction perpendicular to scanning is accomplished by comparing each digitized value of the video signal to a previous value from the same line. When the amplitude of this difference exceeds a predetermined amount a pulse is generated. A predetermined number of these pulses are shifted into a shift regisker. The pattern of pulses skored in the shift register is examined to generate a signal ~17,229 indicative of the central portion of the change ln the gray scale. ("Centra] portion" is used to indicate that the exact center of a change in gray scale is both difficult to define and detect.) This slgnal ls used to generate another digital signal having an ad~ustable time duration which drives a printer to generate a line segmenf, having a pre-determined length and a direction perpendicular to the direction of scanning.
The digital numbers representing the instantaneous values of the video signal at the sampling time are also stored in a digital memory. Sufficient memory is provided to store digital numbers representing several lines~ typi-cally eight, of the video signal. Changes in the gray scale having a direction parallel to the direction of scan are detected by comparing the digital number representing each sample of the video signal to a corresponding digital number from a previous line. When the clifference between these two signals exceeds a predetermined amount a one bit digital pulse signal is produced. A predetermined number of these pulses are shifted into a shift register. The pattern of pulses stored in this shift register is examined to generate a signal indicative of the central portion of the change in gray scale. ("Central portion" is used to indicate that the exact center of a change in gray scale is both difficult to define or detect.) This signal is used to generate another digital signal which also drives the same printer to produce a line segment on the printer having a predetermined width and a direction parallel to the direction of scan. The combination of the two line segments results in a line drawing being produced by the printer with the lines corre-47,229 sponding to changes in the gray scale of the scanned image.
The llne drawing representing the changes in gray scale may be printed in either posltive or negative format.
That isg the changes in gray scale can be printed as ~lack lines of predetermined width on a whlte background or they may be printed as white lines of a predetermlned ~idth on a black background.
DESCRIPTION OF THE DRA~lNGS
Figure 1 i3 a functional block dlagram of the preferred embodiment of the invention.
Fig. 2 is a block diagram of the digitizer used by the system.
Fig. 3 is a block diagram of the memories used to delay the video samples to detect; changes in the gray scale ; in a direction perpendicular to the direction of scan.
Fig. 4 is a diagram of the clrcultry used to detect changes in the gray scale to generate llne segments perpendicular to the direction o~' scan.
Fig. 5 is a block diagram of the memories used to delay samples of the video signal to detect changes in the gray scale parallel to the direction of scan.
Fig. ~ is a diagram of the circuitry used to detect changes in the gray scale in the direction parallel to the scan.
Flg. 7 is a block diagram of the memories used for generating a signal to cause the prlnter to produce line segments corresponding to changes in the~gray scale in the direction parallel to the direction of scan.

Fig. 8 is a circuit dlagram for combilling the signals indicative of changes in the gray scale in both the 47~229 dlrection perpendicular to the scan line and parallel thereto to generate a composite signal to drive the printer.
DETAILED DESCR-LPTI0~
Fig. 1 is a block diagram of the preferred embodi-ment of the invention. The system lncludes a scanner 20 which scans an image, for example, a photograph. The scanner 20 may be any suitable type of scanner, for example, a TV camera or a laser-type scanner. In the preferred embodiment scanner 20 is a laser which scans the image to produce a line of video information each time the image is scanned.
Each line of video information from scanner 20 is coupled to an eight-bit analog-to-digital converter 21. A
clock signal is also provided by scanner 20 to the analog~
to~digital converter 21 permitting each line of video in-formation generated by scanner 20 to be sampled to generate 4,og6 digital numbers with each number representing the instantaneous amplitude of the video signal from the scanner 20.
The output data of the A to D converter 21 is stored in a shift register memory 22. In the preferred embodiment each sample of the video signal generates an eight-bit digital word at the output of analog-to-digital converter 21. Eight digital bits for each sample are avail-able at the output of analog to-digital converter 21 and are stored in a shift register-type memory 22. The shift regis-ter memory 22 has sufficient storage capacity to store digital numbers representing eight samples of the video signal from the scanner 20. Shift register memory 22 is arranged such that the data stored in each stage of the 47,229 shlft register is aval:lable as an input to a multiplexer 23.
A dlgltal delay select, signal is also coupled to multiplexer 23 to select the outpu~, signals of the shift register 22 which are to be coupl,ed to the output termlnal of multi-plexer 23 to generate a digltized and delayed version of the video signal appearing at the input of the analog-to-digital converter 21.
Changes in the gray scale of the image being scanned by scanner 20 are detected by an edge detector 30.
Changes in the gray sca:le are detected by edge detector 30 by comparing the amplitude of' the delayed digitized version of the vldeo signal appearing at the output of multiplexer 23 to the output of the analog-to-digital converter 21 to generate a signal indicat,ive of the absolute difference '' between these two signals. This absolute dif`ference is compared to a threshold signal to generate a one bit digital signal indicating that t;he absolute difference is either above or below the threshold. A predetermined number of the bits of this signal are shifted into a shift register which is included in a diff'erence detector 31. Digital informa-tion stored in -this reglster is used to detect the center of gradual changes ln the gray scale of the image being scanned.
Out--of-focus edges in the scanned image is an example of a gradual change in gray scale. (The operation of this cir-cuit will be described in detail later.) In some applica-tions it may not be necessary to detect out-of-focus edges.
However, if it is desired to make an accurate line drawing of an object from a photograph which includes out-of-focus edges, some technique must be used to detect the center of these edges.

i3~
47,229 In the preferred embodiment of the invention the shif't register included ln the difference detector 31 into which the bits of the dlgital signal indicating that the difference between the delayed version of the video signal and the video signal exceeds the threshold is shifted is eight bits long. This permits the eight bits stored in the shift regis~er or these bits and ~he output signal of the edge detector 30 to be combined to determine the center of changes in the gray scale of the image being scanned. In either case~ when all of the bits being considered form a symmetrical pattern, an output signal is generated. This output signal is coupled to a pulse width generator 32. The outpu~ of' the pulse width generator 32 is a pulse indicating the width and position of the vertical line segment to be printed b~ the printer 44 corresponding to the detected change in the gray scale of the image being scanned.
The eight~bit output signal of the analog-to-; digital converter 21 is a]so coupled to the input of a second series of shift registers 33. Included in the series o~ shift register 33 is a shift register ~or each bit o~ theoutput signal of analog-to-dlgital converter 21 with each o~
these registers being long enough to store digital data representing eight lines of the video signal from the scan-ner 20.
The registers 33 are arranged such that the stored data representing each line serves as an input to a line select multiplexer 34. A three~bit digital line select signal serves as a second input to line select multiplexer 34 to select the appropriate input signals to generate at the output of this multiplexer a digital signal spaced from 3~
1l7,229 the real time v:Ldeo signal by the selected number of lines.
Edge detec~,or 40 subtracts the delayed lnformation f'rom the multiplexer 34 from the real tlme information output at analog-to-digital converter 21 and takes the absolute value of this dif~erence to generate an output signal which is coupled to difference detector 41. Difference detector 41 compares the output signal of edge detector 40 to a thres-hold signal and generates a one bit digital signal indicat-ing when this signal exceeds the threshold. A predetermined number of the bits of this signal are shirted into a shift register. The pattern of pulses stored in this shift regis-ter ls examined to generate a signal indicative of the center of the change in the gray scale of the image being ! scanned. The output signal from this circuit is coupled to `; a pulse width generator circuit 42. This circuit generates a signal which is coupled to the combining circuit 24 to generate a signal which causes the printer 44 to print a horizontal line segment having a predetermined ~idth.
The sampling rate of the analog-to-digital con-verter 21 is controlled by a clock signal provided by the scanner 20. Additionally, the scanner 20 provides a blank-ing signal during the retrace time which is also coupled to the combining circuit 24 to disable this circuit during the retrace. Additionally, the analog-to-digital converter 21 generates a pulse indicating that each sample has been converted to its digital equivalent and that this digital equivalent is available at the output of analog-to-digital converter 21. These signals are coupled to a clock gener ator circuit 43 to generate control signals for controlling the memories and other circuits previously described.
_9_ ~6S33 47,229 Fig. 2 is a more detailed block diagram of the analog-to-digital converter and the clock generator. The video signal from the scanner 20 is coupled to the analog input of an analog-to-digital converter 47. The clock signal from the scanner 20 ~hich specifies the sampling rate ~s coupled to the input of a 70 nanosecond pulse generator circuit 48. The blanking signal from the scanner 20 i6 coupled to the disabled input of this circuit to prohibit the generation of pul~,es during the blanking interval. This arrangement permits the cloc~ signal specifying the sampling times from the scanner 20 to be free running and reduces the memory space required because the memory shift registers 22 and 33 (~ig. 1) are not shifted durlng the blanking interval.
The output signal of the 70-nanosecond pulse ; generator 48 is coupled to the sample input o~ the analog-to-digital converter 47. Each output pulse of the 70--nanosecond pulse generator 48 causes the analog-to-digital converter 47 to sample the video from the scanner 20 to generate an eight-bit output signal corresponding to the amplitude of the video signal from the scanner at the time of the sample. When sampling is complete the analog-to-digital converter 47 provides a trigger signal to a 500-nanosecond pulse generator 49. The blanking signal from the scanner 20 is also coupled to this pulse generator to dis-able the circuit during the blanking interval. Two com-plementary output signals are available from the 500-nano-second pulse generator 49. One of these signals is coupled to the clock input of two flip-flop memories 50 and 51.
This causes these flip~flops to be set to values correspond-ing to the output of the analog-to-digital converter 47.

47~229 This results in gerleratlng a digital number at the outputs of these two memories corresponding to the output of the analog-to-digit;al converter 47. The output bits of these memories have been labeled HV0 through H~7, with HV0 being the most significant blt. These are the output signals from the A/D converter, illustrated functionally in Fig. 1. The inverted outputs are lndicated by a "bar", in the conven-tional manner. These memories are synchronized with the clock signal generated by the 500-nanosecond pulse generator circuit 49.
The second output of the 500-nanosecond pulse generator circtlit 49 is inverted by a buffer gate 52 to generate a high speed (HS) clock signal. A flip-flop 53 also receives the output signal of the 500-nanosecond pulse ; generator circui-t 49 to divide this signal by two to gen-erate a second low speed L,S clock signal. The use of these signals will be described in more detail subsequently.
Fig. 3 is a more detailed diagram of the shift register memory 22 and the multiplexer 23 (Fig. 1). As previously explained 3 the shift register memory 22 (Fig. 1) is actual]y eight individual shift registers. These eight-bit shift registers are illustrated at reference numerals 58 through 65 (~ig. 3). Each register, 58 through 65, is capable of storing eight bits of digital information. The inputs to these eight registers are the bits of the digital numbers representing the amplitude of the video signal from the scanner 20. The digital numbers representing the video signals are provided to the input of these registers by coupling the data input terminal of each of the eight-bit shift registers, 58 through 65, to the appropriate ou-tput 53~
l~7,229 terminal of flip-flop memories 50 and 51 (Fig. 2). Input sîgnals to these shift registers are labeled HV0 to HV7 to correspond to the signal designations used in ~ig. 1. Data is shifted into these shift registers by coupling the clock signal terminal of each of the shift registers~ 58 through 65, to the high speed clock signal derived f'rom the output of an inverter 52 (Fig. 2). As previously explained, this clock signal includes a pulse which immediately follows the setting of flip-flop memories, 50 and 51. This causes an additional bit of digital data to be shifted into each of the shift registers9 58 through 65, for each cycle of the analog-to-digital converter 47 (Fig. 2). Since the shift registers, 58 through 65, are only eight bits long, only eight samples of the video signal from the scanner are ; stored in these shift registers.
Shift registers 58 through 65 are designed such that the data stored in each stage of these registers is available as an output signal. These output signals are coupled as inputs to eight multiplexers, 70 through 77. A
three-bit digital line select number specifying the delay desired is coupled to the second input of each of the multi-plexers, 70 through 77, to select which of the inputs are to be coupled to the output. This permits the generation at the output of these'multiplexers, 70 through 77~ a dlgital signal which is a delayed digital version of the video signal coupled to the analog-to-digital converter 77 (Fig.

2). The selected digital value and its c,omplement are available at the outputs of multiplexers 70 through 77. The availability of both polarities of this signal simpli~ies the comparison of this signal to a selected threshold as ~6533 47,229 will be subsequently described.
~ ig. 4 is a more detailed diagram of the edge detector 30g difiference detector 31 and pulse width gener~
ator 32 illustrated at reference numerals 30, 31 and 32 of Fig. 1. A digital number corresponding to the amplitude of the video signa] at the last sampling interval is available at the output of flip-flop memory cirCuits 50 and 51 (Fig.
2). A dig~tal number corresponding to the amplitude of the video signal at selected previous sampling interval and its complement are available at the output of eight multiple~ers~
70 through 77 (Fig. 3). The output signals of flip-flop memories 50 and 51 and the complement of the selected delayed sample from the output of multiplexers 70 through 77 are coupled to the input of two four-bit adder circuits 3 80 ; and 81, (~ig. 4). The output of these adders, 80 and 81, are inverted by eight inverter circu:lts, 82 khrough 89. The inverted output of the adders, 80 and 81, along with the output of the adders, 80 and 81, are combined in two mul~l-plexer circuits 95 and 96 to generate an eight-bit digital number equal to the absolute value of the difference between digital numbers representing the current and delayed samples of the video signal. This absolute value of the difference between the two inputs is compared to a threshold by a comparator 97 to generate a signal indicative of the ampli-tude of the input signal relative to a predetermined thres-hold. When the absolute value of the output of the two adders, 80 and 81, exceeds the threshold, a one bit logic "one" signal is generated and shifted into an eight-bit shift register 99. If the change in contrast causing the logic one outputs from the magnitude comparator module 97 is 47,229 not sharp the logic one output signal from this comparator 97 may be present for several clock pulses prohibiting khe detection of the precise center of the gray scale change in the image being scanned by presence or absence of this signal.
A change in the gray scale is lndicated by all of the bits stored in this register being logic "ones" or by the control bits having a logic "one" level surrounded by a symmetrical pattern of logic "zero" bits. Normally the threshold is selected such that the shift register 99 is not completely filled with logic "one" bits. Therefore, the central portion of the change in gray scale is indicated by the central bits being logic "one" surrounded by logic "zero" bits.
; More specifically, the first and last bits of shift register 99 are coupled to be inputs of a first ex-clusive OR circuit 100. Similarly, the second and seventh bits, the third and sixth bits are coupled to the inputs of two additional exclusive O~ circuits 101 and 102. The fourth and fifth bits of the eight-bit register are coupled to the inputs of an AND gate 103. Thus, so long as there is a symmetrical pattern of one bits stored in the eight-bit shift register 99, the output signals of exclusive OR's 100, 101 and 102 and AN~ gate 103 will all be logic ones. The output signal of all these gates are combined in a four input AND gate 104 to generate a signal indicating that a symmetrical pattern of one bits with at least the fourth and fifth bits being logic ones are stored in the eight bit shifk register 99. Additionally~ if the input signal to the eight-bit shift register 99 is considered 3 it is possible to -14~

47,229 have a sy~etrical pattern of bits stored in thls register with only one logic "one" bit or an odd number of logic "one" bits. These patterns o bits are detected by eoupling the fourth bit of the shift register 99 to one input of a NAND gate 110. The output of the comparator 97 and the eight bit of register 99 are eoupled to the inputs of an exclusive OR gate 111. Similarly, the first and seventh, second and sixth, third and fifth bits form inputs to exclusive OR gates 112 through 114. The output signals of four exclusive OR gates, 111 through 114~ also form inputs to NAND gate 110. The output signal of AND gate 104 is inverted by an inverter 115. Output signals from the inverter 115 and the NAND gate 110 are eombined in a NAND
gate 116 to produce a logic signal indicating that a sym-metrical pattern of logic '1one" and logie "zero" bits are stored in the eight-bit shift register 99. This eorresponds to the center of a change in the gray scale of the image being scanned. The circuit described above consisting of a shift register 99, six e~clusive OR gates 100, 101, 102, ?0 111, 112, 113 and 114, two AND gates 103 and 104, two NOR
gates 110 and 116, and an inverter 115 is a circuit whleh, as previously described, enables the deteetion of the eenter of a change in the gray scale of the image being seanned.
This center detector circuit 175 is also utilized by another section of the system of this use will be described later.
The signal indicating the eenter of a ehange in gray seale of the image being seanned is eoupled to the enable input of a triggerable flip-flop 117. This eauses the output of this flip-flop to go to a logic "one" on the leading edge of the first eloek pulse of the high speed ;53~
47~229 clock signal following detection of the change in gray scale of the image being scanned. The complementary output of this flip-flop 117 forms a first input to a NAND gate 118.
The second input to this gate i5 the output of NAND gate 116 which indicates detection of a change in gray scale. Com~
bining these two signals in NAN~ gate 118 generates a logic one signal having a duration equal to the period of the high speed clock signal for each change in gray scale detected.
This signal is coupled to the first input of a four-stage counter 125. This enables this counter to be preset to the value of an external digital line width selection signal which specifies the line width of vertical line segment to be produced by the printer 44. Additionally, this signal permits a line width flip-flop 126 to be set. Setting of the line width flip~flop 126 generates a logic one at the output of this flip f:lop which will ultimately enable the printer 4~! to pr~int a line segment corresponding to the detected change in the gray scale of the image being scanned.
~; The complementar~ output of this flip-flop is also coupled to an enable count input terminal of counter 125 enabling this counter to be incremented by the high speed clock signal. Once counting begins, counter 125 continues step-ping until it reaches its maximum value. When this value is reached a gate 127 receives a signal indicating the maximum count has been reached. This signal turns on this gate and resets the vertical width flip-flop 126. Resetting of this flip-flop also disables the pulse width ~counter 125 to disable the printing of vertical lines by the printer 44 ~ (Fig. 1?-In addition to the mode of operation described Ll 7 , 2 2 9 above, circuitry is included which permits the transitions in the gray scale from black to white or the transitions from white to black to be inhibited. The input to adders 80 and 81 are selected such that for transitions from white to black there will be an overflow signal from adder modules 80 and 81. This signal is inverted by an inver-ter 120 and combined with an inhibit white-to-black transitions signal in a NAND gate 121 to generate a signal which inhibits the multiplexers 95 and 96 when these transitions occur. Simi-larly, an inhibit black-to-white transitions signal is combined with the overflow signal from adders 80 and 81 by a N~N~ gate 122 to generate an inhibit signal for these tran-sitions. This feature permits large areas of black or white in the image being scanned to be printed as narrow lines corresponding to the selected transitions.
The circuitry for detecting changes in the gray scale in a direction parallel to the direction of scan will now be described in detail. The output data from flip~flop memories 50 and 51 (Fig. 2 ) are also coupled to the input of eight shift registers. (Two typical registers are illus-trated at reference numerals 130 and 132, Fig. 5.) Eight shift registers are used because each sample of the video signal from the scanner 20 results in eight bits of data at the output of flip-flop memories 50 and 51. Two of the identical shift registers 130 and 132 are illustrated in Fig. 5 with the most significant bit of each of the digital numbers resulting from sampling the video signal from the scanner 20 being stored in the first register 130 and the least significant bit of each of the digital numbers gen-erated by sampling the video from the scanner 20 being ~6~3 47,229 stored in the second register 132. The other bits frorn each of the digital numbers are similarly stored identical shift registers. These registers are not illustrated for reasons of simplicity.
Each of the serial registers is actually comprised of eight serially connected shift register modules. The shift registers are clocked at one-half the sampling speed of the analog-to-digital converter 47. This reduces the amoun-t of data stored in half and is possible because it was not felt that the resolution in the direction parallel to the scan ]ine was as critical as the resolution in the direction perpendicular to the scan line. This permits fewer samples to be stored. Additionally, some applications may not require -that the least significant bits of each ; sample be considered. ~n such a case, the number of reg-isters can be reduced.
The eight 2,04~-bit modules comprising the first register are illustrated at reference numerals 129 through 143. As previously explained, the sampling rate of the analog-to-digital converter 47 (Fig. 2) is 4, og6 samples per scan line and if only every other sàmple is stored in the shift registers illustrated in Fig. 5, each scan line will require the storage of 2~048 bits of information in each of the shift registers. For example~ the most significant bit of each of the digital numbers appearing at the output of flip-flop memories 50 and 51 (Fig. 2) is coupled to the data input of shift register module 129 and this register is clocked at one-half the sample rate of the analog-to-digital converter 1~7 by the low speed clock signal. Under these conditions, sufficient data will be shifted into this

3 ~
47,229 register module 129 to completely rill this module durlng each scan line. This process is repeated to completely replenish the data stored modules 129 through 143 every eight scan lines. The least significant bit of each sample of the video signal is similarly stored in a second register comprised of modules 129a through 143a. Identical numbers followed by the subscrlpt "a" are used to identi~y the same modules of the two illustrated registers to ~urther empha-size the identity of these two registers. The other six bits of each of the digital data words available at the outputs o~ flip-flop memories, 50 and 51, are stored in six other additional and identical shift registers, which are not shown as previously discussed for purposes o~ simplicity of illustration.
; Each module of the registers illustrated in Fig. 5 store precisely one scan line of information. Since these registers are continually shifted at one-half the sample rate o~ the analog-to-digital converter 47, (Fig. 1) ~or any sample of data appearing at the output of flip-flop memories 50 and 51 the corresponding sample for the previous eight scan lines is available at the output of one of the modules comprising the shift register. For example, the output o~
module 129 is the corresponding sample from the previous line. Similarly, ~he output from module 143 is the sample corresponding to the current sample but displaced therefrom by eight scan lines.
The output o~ each of the modules~ 13], 1335 135 137, 139, 141 and 143 comprising the first shift register 130 are coupled as inputs to a multiplexer 145. A three-bit digital number is coupled to the input ~f this multiplexer 3~33 47,229 to select the output of one of the register modules, 129 through 143, and its complement to be coupled to the outpuk of the multiplexer lL~5. Thls enables data from any one of the eight previous scan lines to be selected and made avail-able at the output of this multiplexer 145. Similarly, the outputs of various modules of the second register 132 are selected to generate at the output of a second multiplexer 145a samples of the data from a previous scan line as described above with reference to the first register 130.
The complement of the output signal from multi-plexers 1ll5 and 145a are coupled as input data to a memory 151 (Fig. 6). The digital number representing the current ampl:Ltude of the video signal :Ls coupled as an input to a second memory 152. These memories are clocked by the same ; clock signal that shifts the registers 130 and 132~ Fig. 5.
Thus, for each clock pulse a new sample of d~ta is available at the output of memory 151 and memory 152. The output signals of these memories, 151 and 152, are coupled as input signals to two four-bit adders, 158 and 15g. The sum o~ the two digital numbers appearing at the output of adders 158 and 159 are inverted by eight inverters, 162 through 169.
Two multiplexers 170 and 171 combine the output signals of the adder modules 158 and 159 and the output signals of the eight inverters 162 through 169 to produce the absolute value of the difference between the current samples and the selected previous sample. This slgnal is compared to a threshold signal in two four-bit comparat~or 172. Whenever the absolute value exceeds the threshold signal indicating that a significant change in the gray scale of the image being scanned is detected a one bit logic "one" signal is l~7,229 generated at ~he output o~ the four-bit comparator 172.
This signal is shiftecl into a center detector circuit 175 to generate a signal corresponding to the central portion of the change in the gray scale of the image being scanned.
(The details of this circuit were previously discussed with reference to Fig. 4.) The output signal of the center detector circuit 175 is coupled to one input of a two-input NAND gate 180 causinK the output of thls gate to go to a logic "zero" indicating that a significant change in the gray scale in a direction parallel to scanning has been detected. Circuitry is also included which inhibits detec-tion of transitions from white to black or black to whlte from being dekected. The overflow signal from adders 158 and 159 is inverted by an inverter 146. The inverted over-flow signal is combined with the inhibit black~to-white signal in a NAND gate 147 to generate a gate 147 to generate a signal which inhibits the output of the multiple~ers 170 and 171 for black-to-white transitions in the image being scanned Similarly, the inhibit white-to-black transitions signal is combined with the overflow signal from adders 151 and 152 to generate a signal which inhibits the output of multiplexers 170 and 171 for white-to~black transitions of the image being scanned. This function is identical with the similar circuit described for the verkical detection circuit (Fig. 4).
The output signal of the center detector circuit 175 is also coupled as an input signal to a 2,048~bit shift register 181. The output signal of the shift register 181 is inverted by an inverter 183 and coupled to the second input of NAND gate 180. This causes the output signal of 47,229 ga-te 180 t~ go low whenever a significant change ~In the gray scale is indicated by the output signal of the center de~
tector circuit 17~ and at a time exactly one scan line later. This assures that any detected change in the gray scale in a direction parallel to the scan line will be reduced in duration to two scan lines.
The output signal from NAND gate 180 is coupled as an input signal to an inverter 184 (Fig. 7). Inverter 184 inverts this signal and provides an input signal to a 15-stage shift register with the stages of this register illus-trated at reference numerals 187 through 201. Each stage of this shif't register has 2,048 storage locations and is shifted by a clock signal coupled to the input of inverter 206. This causes each of the pulses from gate 180, (Fig. 6) ; indicating a change in gray scale and horizontal direction has been detected, to be repeated during subsequent scan lines at the output of a stage of` this shift register with the maximum number of lines the signal is repeated being e~ual to fifteen. The output signals from each of these shift registers is combined in a gating circuit to generate a signal indicating the width of the line segment to be printed when a change in the gray scale of the image being scanned in a direction parallel to the scan direction is detected. The detailed operation of this gating circuit is described below.
The output signals of the shift registers 187 through 201 are respectively coupled to the first input terminal of fifteen NAND gates 220 through 235. ~its one through fifteen of a fifteen-bit line width select signal are respecti~ely coupled to the input of an amplifier 240 47,22~

and the first input or ~ourteen AND gates 241 through 254.
The output signal of an inverter 2~0 and the fourteen AND
gates 241 through 254 are respectively coupled to the second input terminals of the fifteen AND gates 220 through 234.
The output signal of the inverter 240 is coupled to the second input terminal of an AND gate 241. Output signals from AND gates 241 through 253 are respectively coupled as input signals to AND gates 242 through 254. An inverter 270 inverts the input signal to the first shift reglster 187.
NAND gates 220 through 235 and inverter 270 are connected in a wired "OR" arrangement to generate at the output terminal of these gates a signal defining line segments to be printed by the printer 44. This segment will be repeated for one line if the bit of the line width signal coupled to the inverter 240 is a logic "one" and all other bits of this signal are logic "zero". The printed segment will be re-peated for two scan lines if the bits of the line width selector signal coupled to the input of ampli~ier 240 and AND gate 241 are logic "one" with all other bits logic "zero". Similarly, each line segment can be repeated for up to fifteen lines by selecting the logic level of the bits of the line width select signal.
The horizontal and vertical output signals are coupled to the two inputs of a NAND gate 271 (Fig. 8) to generate at the output of this gate a logic "zero" signal when a change in the gray scale of the scanned image in either a horizontal or vertical direction has been detected.

This signal is inverted by an qnverter 272. The output signal of this inverter 272 and a "normal signal" are coupled as inputs to a NAND gate 273. A "reverse signal"

47,229 and the output signal of a NAND gate 271 are coupled to the input terminals of a second NAND gate 27LI~ Output signals from the two NAND gates 273 and 274 and a blanking signal from the scanner 20 (~igo 1~ are combined in a three-input ~AND gate 275. The output signal of this gate is inverted by an inverter 276 to generate a video signal to operate the printer 44. The printed image will be either "normal" or "reversed" depending on the status of the normal and reverse signals; 1'normal" being defined as a black line on a white background for change in the gray scale of the image being scanned. "Reverse" is a white line on a black background.
It will be recognized by those skilled in the art that the techniques described above can be used to analy~e changes in amplitude of any time dependent signal. The ; video signal produced by scanning an image to detect changes in the gray scale of the scanned image is one example of such a time dependent signal.

-2~

Claims (8)

47,229 CLAIMS:

1. A system for scanning an image to detect changes in the gray scale of the image being scanned comprising:
a) a scanner for scanning said image to produce a plurality of lines of video information, said plurality of lines of video information comprising a video signal rep-resenting said image being scanned;
b) delay means for delaying said video signal by a predetermined amount to produce a first delayed video signal;
c) means for comparing the amplitude of said video signal to the amplitude of said first delayed video signal and for generating a plurality of pulses with a pulse being generated each time the absolute value of the differ-ence between these signals exceeds a predetermined value;
d) storage means for storing a predetermined number of said pulses;
e) circuit means for examining the pattern of said stored pulses to generate a signal indicative of the central portion of the change in gray scale represented by said stored pulses.

2. A system for scanning an image to detect changes in the gray scale of the image being scanned in accordance with claim 1 wherein said delay means includes means for digitizing said video signal to produce digital numbers and digital storage means for storing a predeter-47,229 mined number of digital numbers, each of said digital num-bers being representative of the amplitude of said video signal at a predetermined sample time; and read means for selectively recovering said digital numbers to produce said first delayed video signal.

3. A system for scanning an image to detect changes in the gray scale of the image being scanned in accordance with claim 2 wherein said means for comparing said video signal to said first delayed video signal com-prises an adder for adding said digital numbers representing said video signal to the complement of said digital numbers representing said first delayed video signal and a logic circuit for combining the output signal of said adder to produce a digital number equal to the absolute value of the difference between the digital members representing said video signal and the said digital numbers representing said first delayed video signal.

4. A system for scanning an image to detect changes in the gray scale of the image being scanned in accordance with claim 3 wherein said storage means for storing a predetermined number of said pulses is a shift register.

5. A system in accordance with claim 4 further including means for selectively recovering said stored digital numbers to generate said first and second delayed video signals and means for comparing said first and second delayed video signals to said video signal to independently detect changes in said gray scale in a direction parallel to 47,229 scanning and in a direction perpendicular to -the direction of scanning.

6. A system in accordance with claim 5 further including means for producing a first line segment of predetermined length for each detected change in the gray scale in a direction perpendicular to scanning, said line segment comprising a portion of a line drawing.

7. A system in accordance with claim 6 further including means for producing a second line segment of a predetermined length for each detected change in the gray scale in a direction parallel to the direction of scanning, said first line segment comprising a portion of a line drawing.

8. A system in accordance with claim 7 wherein said first and said second line segments comprise a line drawing with the line of this drawing corresponding to the detected changes in the gray scale by said image.