CA1116262A - Modular block unit for input-output subsystem - Google Patents

Abstract

MODULAR BLOCK UNIT FOR INPUT-OUTPUT SUBSYSTEM
Abstract of the Disclosure A modular interface unit to serve as a building block in the framework of an Input-Output Subsystem of a digital data processing system. The unit, designated as a base Module, manages a group of Intelligent I/O Interface Control units (Line Control Processors) and provides a Base module distribution-control interface called a Distribution Card unit. A group of Line Control Processors have a common set of backplane connections to the distribution-control means and to a maintenance unit and termination control unit.
The maintenance unit permits the exercising and diagnosis of any selected Line Control Processor on the Base Module.
The termination control unit provides clocking and control functions for all of the Line Control Processors within the Base Module unit. The base Module unit provides a building block by which a central processing unit of a digital data processing system may be expanded to handle a large number of peripheral devices with simplicity and reliability.

Description

-Cross Re~e~ence to Related ~ cations The ollo~ing commonl~ assigned~ concurrently filed p~tent application is related to the subject matter of this Application:
Serial Number 286,459 ~iled September 9, 1977, for Input Output Subsystem for Digital Data Processing System.
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Field of the Invention This in~e~tion relates to digital computing and/or data processing systems and is concerned with the means and methods of controlling the transfer of data between a variety of different peripheral de~ices and the main memory of a central processing unit or main system. Basically the system involves taking the load off of the processing unit and distributing it among a variety of Intelligent I/O
Interface units which can work independently of the centra;
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processor in handling data trans~er operations.
The invention involved herein describes an organized de~ice, designated as a Base Module, which houses and j supports a plurality of Intelligent I/O Interface units ! within an integrated ~nodular structure. This sub-unit or Base Module comprises a basic puilding block which can be ~ used as a plurality of mod~lar units to build up a system ` around a central processing unit for handling a large 3 number of peripheral devices independently of intervention ' by the central processor.

.~ ' . ~2 roun~ of -the Invention The general configuration o~ ~ d~ta processing system . t~pically comprises a processor or processors, a nlain memory, and a plurality of various types of peripheral devices or terminals (sometimes called I/0 uni-ts), which more speci~ically may be car~ readers, magne-tic tape llnits, card i punches~ printeFs, disk files, supervisory teI~inals, and so on. ~he optimum systems generally invol~e the configuratian ; ~he,rein the peripheral de~ices are handled 'by inde~endent interface control units so that the processor is free to access and process data contained in t:he main mernory. In configurations having separate control means for the peripheral input-output devices, it is possible to ha~e parallel or concurrent processi.ng occurring at the same time that input-output (I/0) operations occ~r~ Th~se co~c~rrent processing I/0 operations occur within the same program which operates through one of the processors, and which also înitiates all input-outp~t operations. In addition the program must have so,me means of determining when t~e I/0 ! 20 operations are inactive or have been completed.
i' As ~n example, if a prcgram calls for a file~of dat.a to be loaded into the main memory, it mus~ be able to de.terr,.-~ine when that operation has been completed before it, c~l ~o a~d to make use o~ the data. m us 3 an inpt~t-output opera~ion is initiated or started by the program, as by some type of "initiate instruction" which prc~ides 3 typically, an address `~ pointing to an ~ 0 descriptor'l wh1ch is stored in the main memory. This descr.i.ptor jdentif'ies the peripheral device from which data is to be recei~ed and/or transmitted, it ,.

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identifies the type of operation such as a "Read" or a ; "Write", and z~lso identifi.es the :Eield of main memory locations to be used in the i~lpUt-output operation.
Generally this I/O descriptor is transferred to a control .. 5 means (I/O control means) to control the transfer of data `i between the peripheral terminal device a.nd th.e main memory.
When the input-output operation i9 "complete1', such as by the transfer of the data from the peripheral unit to the . m~in memory to load the main memoryj then there is a need for some type of a completi.on statement, which is typically ~~ referred to as a "Result Descriptor". Usually this is transfèrred from the I/O control means to some specific location in main memory ~nown to the pr~gram being used~
Typically, the Result Descriptor includes info~nation identifying the particular peripheral terminal device and further incl~des information as to the result of or the ~tatus of that particular input-output operation, -- thus, to pro~ide information as to whether the transfer was complete and correct, or ~.~hether a.ny exception conditions ~o occurred or whether any errors occurred or any other r paculiar sltuations arose in regard to the transaction :~! involving that particular peripheral terminal device.
~ hus, wh~n a program initiates an input-output operation, the program mllst have some means to determine when the input-`` output operation has been completed. A s-tandard techni~ue in this respect is for t.he program -to have instructions to interrogate the Result Descriptors periodically, to determine whan ~and i.f a particular input-output operation ha.s been .
completed. However, it :i9 r.nuch simpler if the input-output .
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coR-~r~l mean.s indicates when the ~ra~lsfer operati.on is ~inished. In .accon;plis~i,ng this, it is usually necessary to interrupt whatever opera-tion the proces:,or has underwa-~, and force it to examine the Result Descriptors and to take appropriate action. This stopping or interruption of the proce~sor~s activities is Oenerally designated as an . "Interrupt".
~ . Thus, when an interrupt occurs~ the processor must stop :~ the-program it is working on, it must make a fi~ed notation ; 10 of what point, in the program execution it was interru~ted arld it must then store the contents of certain registers and control -flip-flops so it can have information as to where it should return in the program after the completion of the interrupt cycle; and then the processor must transfer its , 15 attention and operation to the program designed to handle j and service the Interrupt condition.
! Certain systems such as the system described herein, ~, ha~e a program for servicing ~ t,erruptl' conditions, which progra~ is sometimes referred to as MCP or'a master control ~' 20 program. This program must keep a record of current input-R, output operations and associate the particular Interrupt with th~ part~cular input-output operation tha* caused it.
~ Then it must analyze the results of this Interrupt cycle to i~ see if any un~ual circums-tances ~r -exceptions occurred or

2~ . if an error condition was reported, so that corrective and . appropriate action may be t2keYl. The Interrup-t program ~ must take the res~lts of the input-output operation and '. make~them availabla t,o the program that initiated the input-output operation and t~len ~urther dstermine if other input-. .

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outpu~ cperations are waiting to be initiated and, if so, ~, -to take action to initiate other needf'ul input output operations.
In many of the prior and present system configurations, many calls or request for ~emory access would come in to get memor~ ser~ice~ but because of the limi~ed ban~pass an~ time available for -t~arious peripheral uni-ts, many I/~ transfers would be incomplete and cause "access errors".
Also many of the prior art system conf`igurations provided only one or two communication paths or c~a~ els to ~ ~1titude number of peripheral terminal units so that I/0 transf~rs of a particular peripheral terminal unit had to wait their turn in sharing access and use of a communica-tions bus. This introduced congestion and delay into the system. It al~Q
made difficulties in systems involving multi-programming since efforts are made to match a job ha~ing hea~y input-output requirements with another iob that is "processor-bound" and which has only limited input output requirements.
Many of the present day data processing systems have a single communication path or a limited number of co~unication paths between the central processing unit and the perlpheral units. Generally within the communication path there is one or more "input-output cQntrol" means. When an inpUt-QUtpUt path is requested by a processor, the path will onl~ generally become avallable when: the peripheral unit is not initiating `; a transfer operation; the peripheral unit is not busy in a transfer or other operation with the input-output c~ntrol means; the peripheral unit or its input~output control means is not busy with other operations.

'~Ae data-transfer rate of the input-output control means is 7 of course~ a limiting ~actor in the operation of the system since the often slow transfer rate of certain pèripheral units (which are passed through the illpU t output control means) wlll unnecessarily tie up the processor ard ~emory acti~ity to the low speed of the peripheral termi.nal unit.
Thus, many data processing systems have come to be provided with a plurality of input-output control means which include buf~ers, to pe~mit a particular peripheral or group of peripherals to communica~e with the main system.
When there are a plurali.ty of input-output control means (*hrough which pass the communication char~els to i.ndividual peripheral llnits or groups of such units) some prior art systems have used the method of operating the data transfer operation in a sequential fashion so that the ~arious input-output control means take turns in serving the peripherals which are associated with them.
A difficulty arises here in that certain peripheral units an~ their associated input-outpu~ control means are ; busier than others, and certain of the channels involved actually need more communications-time *han they are gettilIg_ A "channel" may be looked at as a communication path between the main system, through the input output control means, o~er to the peripheral unit. Thus, there can occur situations where oertain channels are "short changed" t~ the ' ~xterlt t~at a great number of "access errors" will be i developed. ~ccess errors inYolve -the situation where the data bytes being transferred through the input-output c-~n~Fal , . - .
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means do not corr.prise complete messagre units but consist only of non-usable fractions of ~essage units~ As a result of this, -the central processing unit would ~lOt ~e ge~ting or transferring useflll information and would have to ~e~o~e fixate~ on continually requesting the same input-output ~perations over and over again. Th~s, when the peripheral units-are placed in a situation where they are unable to send or receive an entire message unit or record, th~n the likelihood of access errors occurs which leads to uncompleted cycles in regard to a particu.Lar channel and no s~c~essful - completion of transfer o~ the required ïnformational data, It is desired that the maximum transfer of data occur through the mentioned plurality of input-output contro1 means,and without s~ch access errors which lead to irLcomplete cycles of data transfer (which are unusable~ and t~e time p~riod of ~hich is wasted and of no use, thus tying up valuable processor time~.
Thus, in such a system configuration, problems arise i in regard to how much time should be allocated to each o.
j 20 the individual channels for data transfer opera~ion~ and ¦ the ~urther problem of which channels should be gi~en ~ priority status over the other channels.
'~ Now1 in ~ata processing systems where multitu~es af ~ peripheral units are involved (many of which are at S 25 differently located installation sites) it is necessary to have groupings of input-output control means to han~le the h variety of peripheral units at ~ach given site. Thus, the priority probl0ms involve no-t only t~e priority to be given as to the competition ~mong peripheral ~nits at ~ne loca~ gi~en site, but also involve the priority problems of priority allocation as ~etl~een the dif~erent locational sites, each of which have their o~n inpu~-output control means.
S~marv of the Invention _ _ The present invention involves a digital data processing systeM for the control and handling of inpu-~-olltput operations (data transfers) as between a plurality of various types of peripheral units and a central Main System (Processor and Main Memory). Two types of I/O Subsystems are provided for communication to the central Main System.
One I/O Subsystem is a system wherein a t~pe of intelligent interface control uni-t, designated as a "~ine Control Processor" (LCP), is used, and wherein each LGP, while performing the same basic functions, is specificalIy oriented to control and handle data transfers to and from a specific type of peripheral terminal unit. ~or example, a basic LCP would be adapted ~or each specific instance to handle a card reader, a disk unit, a train printer, or other special type of peripheral unit. The LCP's are placed in groups, typicall~, of eight units, to form anLCP Ba~e Module.
Then each of the Base Modules are grouped in a set of three to form an LCP Cabinet Unit. A plurality of such LCP
Cabin~t Units may be used to constitute the first I/O
~` Subsystem.
2~ ` Another I/O Subsystem is provided for those types of peripheral terminal units for which no specific Li.ne Control Processors (LCP) have been developed. This second I/O
Suhsystem is organized so that a Central Control unit is provided to control the pathing from -the Central Prooessor _ 9 _ _ . , .. _,, .. . . . ... . . -6:~
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and Main Memory to selected input-output channels which provide a data path to individual peripheral units. These individual channels will each have their own memory buffer and connect through the Central Control unit over to the Main System.
In the I/O Subsystem using the Line Control Processors, the Main System (of Processor and Main Memory) is also provided with a unit called an Input-Output Translator unit (IOT) which becomes part of the Main System and provides an interface between the Main System and another distribution-control interface designated as "Distribution Card Unit"
which handles a Base Module, ~a group of Line Control Processors) and which connects a selected individual Line Control Processor into the LCP I/O Subsystem.
The Line Control Processor's (LCP's) are organi~ed in , groups of eight called the LCP Base Module each of which has a single "Distribution Card Unit " which provides the ~ interface between the Input-Output Translator, IOT, of the -, Main System and the Fight LCP's~of any given Base Module.
Each Base Module also carries a Maintenance Card unit which can provide all maintenance and checking functions for the group of eight LCP's of the Bas~e Module. Each Base Module , is also provided with one common "Termination Card Unit"
which provides~common clocking functions for all the LCP's of the group and also provides proper terminations for the j transmission lines which connect the various LCP's, the Distribution Card, and the Maintenance Card of that particular Base Module.
The IOT of the Main System works in a unique relationship with the Distribution Card Unit of the Base Module of the LCP's in the LCP I/O~

`: -- 10 --Subsystem, serving to setup data-transfers between the periphal units and the Ma:Ln Memory in a fashion that does not burden the Central Processor and which permits concurrent data-transfer operations to occur between any number of peripheral units and the Main Memory. This is facilitated by the use of a record-length buffer memory in each LCP. The data-- transfer cycle is accomplished using complete data message-blocks which thus prevent "access errors" from occurring.
The embodiment of the invention described herein provides a system which helps alleviate certain problems inherent in prior art systems. By providing a separate channel from the Main System to each peripheral unit, there is no need for data transfers (between a particular peripheral unit and the Main System) to have to wait for the use of a shared communication channel, since each individual peripheral unit is provided with its own channel, and thus each of the plurality of peripheral units can simultaneously and concurrently consummate input operations without any further requirements from the processor or without interference~to processor operations.~ The input-output data-transfer control means in the Subsystem is provided by an individual "Line Control Processor" (LCP) for each peripheral unit, The "Line Control Processors" accept input-output commands from the Main Memory (via the I/0 Translator unit) and they e~ecute these i I commands indPpendently of the main processor, so that input-.;
I output control operations are performed in parallel with and asynchronously with processing.

; A memory control unit 10 Fig.lA, regulates the flow of databetween the Main Memory, the Central Processor and the I¦0 Subsystem. It allows each of the system components to have access to Main Memory on a priority basis, giving the highest priority to the I/0 Subsystem. Since the memory control operates independently of the Processor, the Processor is free to perform memory-independent functions at the same time that memory accesses are being granted to the I/0 Subsystem.
The Line Control Processors are each provided with memory buffers which can store an éntire message-block or record-length of data. Thus, data transfers between Main Memory and the Line Control Processor can take place at high speed and constitute a complete message-block in itself.
Since a complete message-block of data is transferred in any '~ given cycle, the problem of access errors is eliminated so `! that no further memory cycle tîme is required to complete `! "incomplete former data transfer cycles", which might occur absent the record-length buffer.

The Line Control Processors are functionally the same except that minor variations may occur so that they are adaptable to work with different types of peripheral terminal units, and, as such, the LCP's are "transparent" to the Main System.
In certain cases, there are peripheral units and data j storage devices involved for which no specific Line Control Processors (LCP) have been developed. In this case, there is : used another input-output control subsystem which can operate in parallel with the first I/O Subsystem and its Line Control Processors (LCP).

The main or central system of the described embodiment, which may include the Processor, ~he Main Memor~, and the Memory Control, is furnished with a unit called an Input-; Output Translator or IOT. The IOT i5 a special portion of the Processor which, upon receipt of an I/O descriptor from memory, works in conjunction with the LCP Base Module to establish connection to the particular LCP in the channel specified by the "Initiate I/O" instruction from the program.
The IOT translates the I/O descriptor into a form (Colmmand Descriptor) recognizable to the LCP (Line Control PLocessor), and when connection is established, passes the translated descriptor over to the LCP after which the data transmission may begin. During the time that data is being transferred between the LCP and the Main System, the IOT, upon demand by the LCP, requests memory accesses, addresses memory, then-modifies and compares the data addresses. The IOT controls the routing of data between the selected LCP and the Main System, and it performs translation (ASCII/EBCDIC) of the data~if so required. ASCIIlEBCDIC refers to American Standard Code for Information Interchange/Extended Binary Coded Decimal Interchange Code. Upon completion of an operation, the IOT accepts Result Descriptor (R/D) information from an LCP and then stores the Result Descriptor (RlD~ in a predetermined location.
The Line Control Processor, (LCP), is a device which upon receipt of a Command Descriptor (C/D) from the Main System via the IOT establishes a communication path to a selected peripheral unit. Once this path is established, the LCP
accepts data from or passes data to, the peripheral device.

Since each LCP has a i'data buffer" (-ty~ically 256 words)~
then data ean be transferred to and from the peripheral ~evice at the comparatively low s-pee~ rate of the peripheral device; then, when ~he buffer is full, the data can be transferred to the central Main System at tl~e highes-t rate permitted by speed of the Main Memory. ~luS~ a unique interworl;ing relationship exis-ts between -the IOT (Input-Output Translator) of the Main System and the LCP which is the-interface control between the peripheral units and the Mai~ System. A~urther, a uniq~e working relationship e~ists between each LCP and the Distribution Card Ullit of its Base ~odule, which interfaces a given LCP to ~he IOT of -the Main System. The Distribution Unit not only provides for interconnection of the Main System to a selected LCP but also regulates ~riorities among LCP's for acoess to Main Memory.
The invention particul~rly claimed within the I~O
Subsystem described herein, is a modular interface unit ~ designated as Base Module and which permits grouping of i 20 Line ~ontrol Processors via a local dist~ibution-con-trol ;l in*erface designated as the Distribu-tion Card Unit.
! Some of the major objectives of the Line Cvn-trol Processor I/O Subsys-tem may be summari~ed as follows:
To relieve the Central Processing Unit from getting involved in monitoring and controlling data -transfers between the System~s Main Memory and a large number of perlpheral units.
TQ increase the rate of data transfer between a varlc?ty of different peripheral ~-~nits all connected to tAle ~ai~

3 System having a Main Memory and Processor. This incl~l_ . .
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tX~ns~exs f~o~ the M~in Memox~ to an~.~ndividu~l pexiphexal in this s~stem And Vice ~e~sa, To pxo~ide ~n Intelligent I~O ~nte~ace cont~ol unit CLine Contxol ProcessorL ~hich ~ill xelàeve the Cent~al Pro~
cessor o~ man~ ~uxdens and ~h~ch will ~e responsive to the needs of various periphexal units for access to the Main Memory.
To pxovide an Intelligent Interfacs I~O contxol unit which can recei~e an I~O instruction rom the Central Pro-cessing unit and then independentl~ continue in reyard to controlling,monitoring, and executing this instruction so as to accomplish data trans~er between Main System Memory and any specifically desired peripheral unit.This is done as~nch-ronously as the needs and tha requirements arise~The intex-face unit tLCP~ also handles the error~checking of all word and message block transmissions in addition to keeping the Main S~stem in~ormed of the status of any data-transfer cycle, as to its completeness, incompleteness, error-status- The Line Control Processor also monitors requests from a peri-pheral unit for ~ccess to Main Memory and informs the Main System of "busyness" of the peripheral unit or its unavail-ability, ` To permit easy modular system expansion, the I~O
.~ ~ Subsystem of the Central Processing unit servicin~ a plural-ity of terminal units is set up such that the interface units (Line Control Processor) are organized in Base Modules in groups of eight unitsO Each module has a Dist*ibution Card Unit which interfaces the group of eight Line Control Pxocessors to the Main System Yia the IOT o the Main S~stem. The Distxihution Un~t can thus set ` 1 ~ i l~r ~

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priorities as bet~een any one of the eight ~ine Control Processors in the Base ~lodule. Fur~her7 w~len a.,plurality of Base Modules occur in the System then the Distribution Unit of each Base Module can be given a priority ranking (designated global priority) as between the priority rank granted to any given Base ~odule, within the full set of 'Base Modules. Ihus, another object of the I/0 Subsystem involved is to provide arrangements for setting up Global '` Priority (priority as between Base Modules in the System) and also Local Priority (~riority as to precedence status of each Line Control Processor in the group of eight Line Control Processors in the Base Module).
To eliminate "access errors'l so that all the data required at any given time for the Main System (that is, a message length block of data) is always transmitted and error-checked in one complete cycle without interruption (except under emergency conditions).
To permit the rapid completion of a data-transfer operation as between the System's Main Memory and a gi~en peripheral unit, without interruption or incomplete data-transfer, once a communication channel is established ~except for certain emergencies).
To provide the Main System with the current status of any ~ine Control Processor at all times and the results (complete, incomplete or in error) of any gi~en data-transfer crcle . ~ .
To provide modular building blocks for facilitating the expansion of the System by increasing the number of peripheral devices that can be included in the System in a simple economical fashlon.
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( ``` `3 To provide a~ I/O Subsystem whereby the Central Processor is relieved of executing I/O data-transfer cycles and this work load is distributed throughout t~e s~stem via I/O control units ~Line Control Processors) .grouped in modular block units.
Brie~ nescription of the DrawinFs Ihe I/O Subs~stem described herein and the operati~e components involved will be better understood with re~erence to the following drawings of which:
FIG. lA is a schematic of a Central Data Processing System having two different types of I/O Subsystcms; the two I/O Subsystems are designated as ~a) the Central Control Subsystem (CC) with I~put-Output Contrsllers (IOC) ~ and (b) the Line Control Processor (LCP) Input-Output Subsystem;
~IGS. lB9 lC, lD, and lE, are schematics which indicate ` various components of the Central Control type of I/O
:~ ~ Subsystem;
~IG. 2 is a schematic.drawing of a modular unit of the LCP I/O Subsystem known as the LCP ~ase Module showing its relationship to a variety of peripheral devices;
FIG. 3 is a schematic drawin~ of the ce~tral processing unit of the Main S~stem of the Line Con~rol Processor I/0 Subsystem;
~IG. 4A is a simplified schematic showing the basic connective relationships between the Main System, the Iine Control Processor and a peripheral unit withi.n the Line . ` Control Processor I/O Subsystem, ~IG. 4B is a chart indicating various codes for the various instructions executable by a Line Control Processor, 3 LCP;

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~IG. 4C is a chart sho~ing how four infor~,alional digits (~CD) are organized such that a Line Control Processor can inform the ~ain System of operational :` results via a "Result ~escriptor"$
` 5 FIG. 5A is a chart of digital information (Descriptors) :' used by the Input-Output Translator (IOT) to generate Command Messages (C/M);
FIG~ 5B is a schematic showing the data field boundaries ' of the Descriptors in FIG. 5A;
,~ 10 - FIG. 5C is a block diagram of the Input-Output Translator (IOT) in its relationship to the Main System (Processor and Memory) and to the Line Control Prpcessor (LCP);
FIG. 5D is a chart showing the information array in the ~ IOT Descriptor Register;
A 15 FIG. 5E shows the message level interface between the IOT and the Distribution Card.unit of the LCP ~ase Module . 5~ is a sketch of the IOT scratchpad memory;
~IG. 5G is a sket,ch illustrating the address memory scratchpad of'.the IOT (Input-Output Translator~; ' FIG. 6A is a logic flow diagram of the interface between the Main System and the Line Control Processor (BCP);
~IG. 6B is a generalized block diagram of a Line Control Processor;
FIG. 6C is another generalized block diagram of a Line - 25 Control Processor with detail ln regard to its data buffer memory;, ~IG. 6D is a détailed functional block diagram of the Line Control Processor;

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FTG. 6E is a diagram showing ~he intercoc~er~ting logic and control signals between the Input-Output Translator ~IOT) of tne Main Sys1;em and the Distribution Card un.lt for Line Con~roi Processors ~i.thin a ~ase M~dule, FIG. 6~ is a chart showing the arrange~lent of a message ~lock and the composition of a digital word;
. . FIG. 7A is a logic flow diagram of a Line Cont-rol : Processor which handles a peripheral unit and shows the "status counts" for "Receipt of Instructions";
~IG. 7B is a flow diagram showing how tha Line Control.
Processor handles a "Write" o~eration;
FIG~ 7C is a f1ow diagram showing how a Line Control Processor handles the "Read" operation;
- FIG. 7D is a flow diagram showing how the Line ~ontrol Processor 1ogically handles the Result Descriptor;
~IGSo 7E-1 and 7E~2 toge ther form a logic diagram showing the overall logic flow of the Llne Control Processor.

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Description of the Preferr~d E~bodiment ~ he digital system described herein consists of a Processor, a Memory, a series of Input-Output Cont}ollers (IOC's) forming a first I/O Subsystem ~nd a system of Line - 5 Control Processors (LCP's) that make up a seco~d I/O
Subsystem. The Li~e Control Processors basically handl~
input-output operations for specific peripherals with minimal interference to main processor operations. Further, ~ no peripheral device is "hun~ up" waiting for memory access, A 10 since the LCP for that peripheral is always readily available to service its peripheral.
A ~ubstantial number of prior data processing systems utilize a hierarchical system of Main ~lemory in which a ; large capacity, slow buIk memory must ~ansfer information ~o a small high-sp~ed processor memory before that in~ormation can be used. The presently described system allows the Processor and the I/O`Subsystem to directly access any area of memory9 and since the memor~ size may go . up ~o one-million bytes~ far more information is availabl~
to the Processor without the impo~ition of additional I/O
activity. This system may be provided with high-speed (250-nan~second cycle time) bipolar memory together with an . error correct`ion system. Bipolar memory is not only fast, but is inherently more immune to the typ~ o~ errors that cause program failures. If an error is detected, the error correction occurs during the normal memory cycle and there i~ no additional ti~e required ~or a correction c~cle- Various opera~ing rèlationships between the processors main memor~ and other units ~ the present~system may be found in a Burroughs Corporation publication entitled "Burroughs B 2800/B 3800/B 4800 saries,MS-~ Referencè Manual, Catalog 1090560,Copyright 1976.

Normally, I~O memory cycles account only for a small frac-tion of the total number of memory cycles a~ailable.

~o~e~er~ durin~ periods. o~ hi~h ~O ~cti~it~t the probabil~
it~ of an~ t~o deyices Xe~uesting the same memo~y cycle incre~ses. ~hen, due to sLmultaneous xequests, a device fails to get access to memo~ ~ithin a system-allottad time period, then valuable time is los~ ~hile the operation is retried~
Furthermore, during periods of lo~ I~O activit~ many memory cycles are unused.
The I~O acti~ity pxoblems are solved in the pxesent s~stem by distri~uting the I~O processing among a group of LCP's or Line Control Pxocessors o~ganized into Base Modules of ei~ht LCP's each. In so doing, the Central P~ocessor is only required to initiate the I~O acti~ity and it takas no ~urther xole in t~e Input~Output ~I~O~ operation. The Central Pxocessox initiates the I~O acti~ity through a device called the Input~Output Translator CIOTll The LCP, once initiated, can buffer large amounts of data and, in most cases, an entire message ~lock. At some I point in the operation, the LCP requests an access to memory ¦ and when the access is granted, LCP transfers the in~orma-~o tion from its "word bu~er" to the Memory at the maximum rate of memory operation. Now, i~ the requested access to memory is not granted, LCP continues to fill its word data buffer ~hile waiting for an opportunity to access Memory. Thus, the pexipheral de~ice is now protected against no-activity since its data trans~ere to the buffer of the LCP, which transfers it to the Main Memory without missing a m~mory access perioa.
The result of this method and system is that the peak loads imposed upon the Memory by the demands of I~O acti~ity are eliminatedj instead, the I~O Sub~ystem utili~es those memory cycles that ~ould other~ise be missed. Since this , .
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) method of I/O processin~ is more efficient, the system is more capable of a higher input-output (I/O) data transfer rate and can also support more I/O devices.
In the instant computer system wherein there are two categories of Input-Output Subsystems, that is, the second Subsystem of I/O controls and the first Subsystem of an - Input-Output Translator working with a group of Line Control Processors, the control of the system is facilitated by the use of "descriptor" information which is passed among the ~a~ious unitsO
A "Result Descriptor" is a report to the ~Iain operating ~ystem that describes the manner in which an operation was completed or the reason why the operation could not be completed. The Result Descriptors for the Processor and for t~e I/O control systems are 16 bits (one word~ long. The LCP Result Descriptors may be longer than one word, however, and each bit in the Result Descriptor repressnts the status of some condition that is to be reported to the Main opexating S~stem.
The LCP's (Line Control Processors) and the I/OG's (I/O Controllers) always write Result Descriptors upon ~ompletion of an operation the Processor writes a Result Descriptor only if an error condition was encountered.
Result Descriptors are written into predetermined locations in Memory; for the Processor, the location is address 80, for example.
The Result Descriptors for.the LCP's and the I/OC's are written into locations beginning at the address speci~ied by the equation (CHx20) plus 200, where CH i5 the channel .
;' ' ~ ,rS - 22 -~ ~ 3~

number of th~ ~.nitlat~d device. The IOT Result Descriptor is ~ itten into address 2~C). Af`ter the Result Des~riptor has been written, a~ interrupt is ~enerated.
~C _ esult_De~.cri~tors, R/D: Upon ~he co~pletion of its assigned operatiorl, -the LCP stores a Result Descriptor, ~-hich describes to the Processor the manner in ~hich the operation was completed. An LCP ~esul-t Descriptor may consist of one, two, or three 16-bit wordsO The first Res~lt Des6ri~tor, R/D, is stored in Memory at the locatio~ speci~ied by the equation (CH x 20) plus 10~, where CH is the channel number of an LCP. If more than one word of Result Descriptor infor~ation is to be written ~extend~d Resu~t Descript~r)~ the additional words are stored in the address ~emory of the IQTo .. A~ shown .in the table T below, the first LCP Result ~escriptor word i5 preceded by a l-word link and the channel (IOT) Res~llt Descriptor. Typically, the link is used by the operating System as a~ address to the next Result ~escriptor ~;` to be examined. Table II shows the basic word format ~r data~ word having 4 digits, A~ B, C, D, where each digit ~0 has 4 bits ~nd each character has 8 bits. Symbols are used to designate parts of each digit~.as A8, A4~ A2~ Al~ etc.
~;.`. .
TA~LE I : Result Descriptor ...
. _ ___ __ .
; .I~B~ I~B~ I~B~
. CHANNEL(lOT) . . LCP
. _. RESULT ~ESCRIPTOR LJNK RESULT~ESCRl~OR
.5 . .
~x~O) ~ ;OO' ~1%~0)~108_ _ ____._. . .
, Cha~nelJLC:P l~snlt Descriptor ~ocation in Memory ~ , , .
~ 23 -. .
. .~ .

~ TA~LE II : Datil Word .
.
Digits A B C D

_ One Digit - 4 bits ¦ Al Bl Cl Dl One Charact 8 bits = AB

One Word _ ABCD = 16 bits "
The table III below indicates the fornlat for the I~0 descriptor which is normally stored in Main Memory and then aeeessed in order -to regulate a particular type of Input/
' 0utput operation. As will be seen there are four sylla~les~
j ~herein aach syllable lS composed of 6 digits. These digits r` 15 are numbered D1 - D6, D7 - D12, D13 - D18, Dl9 - D24 9. to indica-te tlle relative positions of each digit. In syllable 1, the digits Dl and D2 a]ways specify the type of input/
~'~ o~tput operation to be perfor~led and are generally called the l'0P-code"~ Digits D3 - D6 are referred to as ''variant digits" in that they spec~fy the various opt~ons that a -specific input-output operation can ineorporate.
Syllable 2 contains the address of the most signific~lt digit (MSDj of the Main Memory section whi~ch is used in this particular lnput/output operation as a memor~ buffer area This buffer area is referred to as the beginning addrrass.
Syllable 3 contains -the address of the~least significant dîgit plus 1 (LSD~1) of the input/output core memory b-u~fer area which is referred to as the "ending address''. The most ~: .

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significant address and the leas-t significant a.ddres~ plus 1 represent the maxlmum memory bo1.lndary limits of a record ~eing transmicted. The lensth of the record may or may not utilize the entire area within t,his li.mit. ~ut ~n att~empt ta exceed this limit causes termination of data transrnisslon to that area.
Syllable 4 is used only for disk file descrlptors and contains the aisk address.
Ihe length of the record may or may not utilize t~e entire area wi.thin the beginning address an~ ending address -limits~ As statedl an attempt to exceed this limit causes termination of data transrnission to that area. For example, `. punch cards may be read into an area greater than ~
characters, that is, with a MSD and an LS~l at 8Q charac:ters apart, or they may be r~ad into an area less t~a~ ~0 characte-s; for example, the record area defined i~ a.
pa~ticular object program reflects 40 charact~rs in a card resder record. Data within colu~ns 1 through 40 Q~ the punch card are stored in the record area of core mem~ry : 20 allocated by MS~ and LS~+l.
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, , System Description: (General~
An I/O 5ubsystem is provided:as part of a digital sy's~em ~nvironment to supply ~eans of communication between a central data processing system and a variety of peripheral devices which are attached to and work within the system.
The peripheral devices which work with the overall digital system herein vary from mass storage devices~ such as disks or disk packs, to system control devices such as the operator's super~iso~y terminal, or to a variety of other peripheral devices such as printers, card readers, card punches, magnetic tape storage devices, and so on.
The I/O Subsystem described herein can be divided into two major subsystem categories, based on the method by which the various peripheral devices are controlled. The first category uses a method which employs I/O Controllers (IOCs) wor~ing in `conjunction with the Processor and a Central "

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.

~ ` 7 ; Contr~l to han.dle I/O acti~i-ty. I~le second cate~y us~s an Input-Output Translator (IOT) in ~lle central proces3ing t~lit ich works wi-th individual units called Line Control - Processors (LCP's~. The units ~own as Line vontrol Processors ase the devices which establi~h a colm~unica~ion path from the System (~lain Memo~y and Processor) to a , specific peripneral devic0. Once the communicat1on path i5 established, t,he LCP can accep~ data from, or pass data to, ~he ~specific peripheral de~i.ce~ for later tra~sm1s~i~n ta the Main 5ystem. 5ince each LCP has a built-in data bu~fer,:
then data Gan be transfer-red to an.d ~rom tho gi~en peripheral ~evice at thc oomparati~e~y low s~eed rate of the ~-e~ice;
howeYer) ~hen the data buffer of the LCP i5 connected to transmit to the Main System Memory asld ProcessQrr the data.
can be tr~nsferred to the ~ain 5yscem at the ~ighe~t ra~e allowed by the ~emory of the Central System.
The ~irst categor~ o~ I/O Subsystems which u~e I~C~
QS an interface from a peripheral to the Main M~mar~ an~
~ Proces~sor has a Central Control ~CC) unit whic~ 1înk~ the I/O chan~el and IOC with the Central Processor a~ Memory.
i T~ese Input-Output Controll0rs accept ins~ruc~îan~ f.ro~ the ! Processcr and they retu~l data information in~ing the reault of -~hat happened regarding that partic~.la~ i~stru~*lon.
This result in~o~mation is placed :in a speci~ie~ IQGatIQn in ~5 the Main Memory.
In the s~cond category of I/O Subsyste~ is +~he ~y~tem ~herein the Proce;ssor and Main Me~ory co~munic&te~via ~n put-Output Translator (IOT)~ -to a gro~p o~ LCP ~a-~e ~lodules~
each Module of which constitutes a unit supporting a ~roup , ~,. . ~,., ,~ . .

.

of 8 Line Control Processors (LCP's). Thus~ an instructio~l from the Processor is translated by the IOT into a specialized set of commands which is acceptable to individual LCP's.
~- After an LCP accepts instructions from the IOT, it will then report back certain "result information" which is stored in a specified location in the Main Memory.
Thus, in this second I/O Subsystem, all communications between the main system Processor and Memory over to a i specified peripheral device are controll~d by an LCP which 10 i~ uniquely suited to that particular peripheral device.
When a Line Control Processor LCP,~or an Input-Output Control means having a CentrQl Control~is installed, it is a~signed a unique number called its "channel numbern. ~or I/O Controls this number corresponds to a word of scratchpad 15 memory located in the Processor. For Line Control Processors (LCP's) this "chaI~lel number" corresponds to a word of scratchpad memory in the Input-Output Translator (IOT~.
To accomplish an input-output operation in the system, an I~O request i5 initiated by an Initiate I/O Instruction 20 which tells the Processor where to ~ind the appropriate I/O
Descriptor in the Main Memory and also which char~el number ~t is intended for. The I/O Descriptor contains the OP code and also the variants for the kind of I/O operation selectsd, and the beginning (A) and ending (B) Main Memory addrèss of 25 the memory area invol~ed.
The Processor accesses this I/O Descriptor and then sends the OP code and its variants to the selected IOC
(firs* Subsystem) or to the IOT (second Subsystem). ~he IOC
or the IO~ verifies the OP code and signifies acceptance or 3 rejection o~ the.request.

(' ! ~ ' , In the first Subsystem the Processor then loads the beginning (4) and the ending (B) addresses into a local register and informs the IOC that the addresses are available. These particular addresses are transferred by the IOC into the scratchpad memory location ~or that designated I/O channel.
In the second Subsystem the IOT accesses the A and the B addresses directly from the memory address lines leading to the Prooessor's ~loc~l register" lOpr,FIG.3, at the time of transfer from Maln Memory and thus the IOT loads its own local scratchpad memory lOpS~
. The access to Main Memory i5 shared by the IOT, the Central Control and the Processor. The highest priority is shared by the IOT and the Central Control~ The timing may be so arranged that each Central Control is guaranteed and limited to every fourth memory cycle (at, for example, 8 ~Hz.). The IOT i~ guaranteed the remaining cycles. When the Central Control is not requesting me~ory, then the IOT
can take all the memory cycles. The Processor takes all memory cycles available on a lowest priority basis.
Thus 9 I/O communications in the system require that the Processor execute an I~itiate I/O Instruction (which may be de~ignated, for example, as OP = 94).- This Initiate Instruction specifies the channel number of the requested device and also the location of the I/O Descriptor in Main Memory. Ths T/o Descriptor specifies the action to be taken by the peripheral device a~d speci~ies the boundaries in Memory of the data field. The Descriptors, and the manner in which they are executed, vary, depending on the method by whic~ the peripherai device i~ controlled.

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an Initiate X~O ~nstxuction i5 ~xecuted ~or a chan-nel containing an I~O Cont~ol C~irst I~O Su~system~, then the Processor sends the Descriptor OP code, variants and a C
address Ci~ usedl to the I~O Control.The ~ ~beginningl and B Cendingl addresses o~ the Descriptor are stored in the Processor's I~O channel address memory. The I~O Control veri~ies that the OP code is valid, then signals the peri-pharal d~vice that a data transfer is to begin.
As was pre~iously discussed, the embodiment of the present digital system involves a duality of Input~Output Subsystems. The second of these involve a Central System with Input~Output Translator ~IOTl, a Base Module having a plurality of Line Control Processors ~LCP) and a plurality of peripheral units; the first I~O Subsystem involves, as seen in FIG. lA, a Central Control unit 12 which interfaces with a plurality o I~O controls 13a and 13b which interface with a plurality o~ paripheral de~ices.l4a and 14b étc~
I The following discussion will involva the ~irst IjO
' Subsystem involving IOC's with Central Controllers, CC.
t The FIG. lB sho~s the system of connecting the I/O
channels with the Processor 10p, and the Main Memory 10m , through the Central Control 12. Logic levels are generated in each I/O channel 100, 101.(FIG.lC~ and combined by Central Control 12 before being sent to the Processor 10p and the ~ain Memory lOm. Other logic levels are generated by the Processor, and within the Memory/ and distributed by Central Control 12 to each I~O control such as 13a~ FIGS~lA and lB.
There are ~lso logic levels which pass through the C~ntral Control 12 with the Central Control performing as the connecting - 31 ~
.

~i , block betw~ell the Processor lG and I/O cha:rmel~,.. Yrior.ity lo~gic, 10 of FIG, lC 3de te-rmines which of the I/O char~els will be allowed acce~-s to the Main Me~ory lO , ,hould more than one channel need acce3s at the s~e tlme.
As seen in EIG. 7C 9 there is incl.uded, as part of Central Control 12, a plu~ in translator which is capable of translating BCL (Burroughs Co~mon Language) data to or from EBCDIC (Ext0nded ,inary Coded Decimal Lnterchange Code) as i* goes to or somes ~rom the Core MemoI~ lO~. The I/O
Co~ltrol units, 1.3 , :L3b, FIG. lA, request Ce,ntral Control 12 to use ~he translator, 12t, FIG. lC~, or to bypas~ it. The tra~s3.atio~ takes p~aoe as da-ta is transferred between the I/O Controt unit, such as 13a, and ~he Main Me~ory lOm.
Additional. time is not required for I/~ operation even 1~ though tran~,lation is neoessary. The translator logic t~n~lates incoming Burroughs.Common Langwage ~BCL3 da-ta in~to EBCDIC (Extended Binary Code Decimal I~terchange Code) data or the ou~going EBCDIC data in-to Burroughs Common Language (BCI.). Those EBC2,IC codes which are not assigned ~0 a BCL code) will cause to be generated a code for a BCL
sym,bol "~
~he Central Control 12 -~unctions as an interface between ~ an I/O challnel and the ~in Memo~y 10m durlIlg ~ystem operation,.
t as seen in FIGS. lB and lC. It deter~:ines the pri.ority of memory accesses~ should more than one channel need access, and it translates data coming to the L/O channel, as lOO, from~Memory 10m or from the I/O cha~nel to Memory. The Ce~traI ~ontrol correlates ~arious:f~mctions o.f the channels~
Ihe sequence o~ events i~ initiated:by the Processor lO ~hen an I~O channel ls needed.

~ 3 When the program being performed has need of a peripheral unit such as 14 or 14b of Fig. LA, the Processor 10p executes the "Initiate I/O Instruction". This instruction reads an I/O Descriptor from Memory 10 and then sends the necessary information to the I/O channel, 100, through Central Control 12. This information contains the type of operation (OP code) and the variant information. The remaining portion of the I/O Descriptor including the beginning (A) and ending (B) addresses, is stored in Address ~emory, 10 , FIG. lC, of the Processor 10 . The channel is selected by the channel designate level (CDL) as seen in FIG. lB, which line comes from the Processor 10 .
Once all the information is available, the I/O) channel, 100, is released by the start channel bus (STCB), FIG. lB, to operate independently. When the I/O channel has been released, it operates as another processor and shares the llain Memory 10 with the main Processor 10 or other channels (FIG. lC).
If the operation being performed involves an "input type"
i 20 peripheral unit 14i such as a card reader, the data is received by the I/O channel 100 seen in FIG. lC, and the data is stored in a buffer C within the I/O channel 100.
The I/O channel then requests access to Main Memory 10 via Central Control 12. This request is processed by the priority logic 10 which controls other requests at the same time. Once access to Memory has been granted to the channel, the information is transferred to Memory 10m. The information may or may not be translated depending upon the I/O Descriptor. The information is then written into the Main Memory 10 at the location specified by t~e ~eginning (A) and ending ~ a~dre~s~s in the Addr~ss Memo~y, 10 m.
I~ it is desired, at some poin~, for data or inform~tio~
to be tr~nsI`erred out -to a peIipheral terminal uni.t~ t.hiC ~.s called an "output" o~eration9 EIG. lD. ~f an ~output"
operation is being performed, a simila~ sequence of e~ents occur~ as before, e~cept that data goes from the Main ~emo~y 10m to an I/0 channel such as 102 of FIG. lD. 1~en ~hen a periphe~al unit as, for ex~mple, a printer 14 needs data, th~ memory access request is made to the Cerltral Contl~oL lZ
via the I~0 c~nnel, 102. ~hen priority is granted to the ~- cha~ne~, the data is re~d fro~n ~lain Memory 10m fr~m the address specif'ied by the beginning and ending addresses located in the Address Memory lOpam; this data is then 1~ t.rans~erred to the I/0 cha~nel buffer C2 throu~h the translator 12t (or bypassed around the translator ~epending upon the I/0 Descriptor). As seen in FIG. lD~ th~ ~t~ i ~han transferred to the peripheral unit 9 such as 14 .
As seen in FIG. l~E the Central Control 12 pro~d~ a~
in~erface to/~rom the I/0 channels, the Processor 10 , a~d the Core Memory lOm. Control information ~rom the Pr~ce~r , 10 is sent to the Central Control 12, where it i5 ~1~tr~buted-,, to each I/0 channel as 100, 101, etc. The C~rltral ControI
12 handles all o~ the Core Memor~ re~ue~s made by th.e I/Q
Control u~its in this fi~st I/0 Su~system. Data ~rom ~ach.
I/0 channe.l, which i~ to be written into Core ~emo~y 10 is placed on the Memor~ Write Bus by t~e Central Control IZ,~ and data wh^ich is to be read from :the Core Memory lQm i5 placed on the Core Memory Read ~ls and distributed to eac~ -L/0 channe1.

` '' 34 ~

When a request i5 ~ade by an I/0 channel unit, the Central Control 12 will obtain the Core Memory address from - the Address ~Iemory location reservcd for that specific I/0 cha~nel. This address is us~d to access ~lain Memory 10m and .
the memory cycle i9 then initiated. The memory cycle could be either a "Read" or"~rite" depending on the specific I/0 operationO
~hen the ~rocessor 10 requests a memory access, the mamory address in~olYed is obtained from the Address Memory lO located in the Processor 10 . rllis address is used p~m p to access Main Memory 10 , and the memory cycle ~either a read or a write) is initiated.
Since only a single memory access can be made at a gi~en moment, multiple memory requests must be handled in~i~idually, and this handling is accomplished automatically ~ia Priority Control 10pc (FIG. lC,lD~ by Central control 12, as pre~iously discussed. Each Central Control 12 contains npriority logic" 10 which is established or changed by a field engineering adjustment. As I/0 channels are added to the Central Control 12, they are also added to the priority net~ork. The Processor lO ,in this casa~ has a lower priority ~han a Central Control 12~ The highest priority request i~
granted first, and as soon as it is completed, the next h~ghest request is automatically granted. This proc~ss is repeated until all of the multiple requests are handlad.
The requests are alternately granted to e~ch Central Control unit (when multiple Central Controls are used) depending on which control was granted the last re~uest~ I~ a Central Control dQes~not want the acce~s, then it is granted to the Processor lOp.

~ 35 . ~ ''` ' .

t ; Du~in~ the cou~e o~ a data tx~ns~er o~er~tion within - the ~irst cate~o~ Su~s~ste~rth~ I~OC ~nput~Output Controllerl may per~orm several ~unctions depending on the OP code, the variants, and the t~pe o~ peripheral device~
Typically, the ~O Controls have the ability to ~uffer onl~
one byte or at mos~ one word. Thus, when the data bu~fer of a control is loadedt the I~O Controller or I~O Channel Unit 100, 101, 102, must request a memory access; there~ore, the rate at which dat~ is transferred to or transferred from the System is controlled primarily by the speed rate at which :
the peripheral de~ice can read or write The second IjO
Subsystem using Base Modules with Line Control Processors does not ha~e this speed limitation~
~hen the I~O Controller xequests a memory access, it is, in efect, asking the Processor to perform a series of ~ operations; these operations include: ~a~ the transfer o ¦ the data field address from the processor's I!O channel address memory to the local address register; (b~ the initia-tion o~ a memory cycle; (c) and the restoration of the data field address-to the address memory of the channelO The i I/O Controller also indicates to the Processor the amount i by which the address must be incremented so as to point at ! the next data field location. Upon completion of the opex-ation, the I/O Controller builds a Result D~scriptor ~R/D~
indicative of how the operation was effectuatad, ~hen the I/OC stores the Result Descriptor in a reserved memory location, after which it sets the Processor Interrupt flip-ælOp, In the second category o~ controlling I/O activity, use is made of an Input/Output Translator ~IOT) interface - ' unit which is located in the central processor unit 10 J~ The IOT interfaces with a 3~ _ ~ 6~

group of-Line Control Processors (LCP) which are installed in LGP Base ~IOdules. Up to eight LCP's may be housed in an LCP ~ase Module. The Ease Module for the LCP~ 9 holds up to as much as eight LCP' 5 . The LCP is an intelligent interface unit which establlshes a buffered data-transfer path between the peripheral device involved and the main system of Processor an~ Memory. This communication path is established by the LCP upon receipt of a Com~and Descriptor (C/D) from the IOT
~-hich has translated an original I/O Descriptor into a ~pecialized Command Descriptor for the LCP.
Since each LCP has a large "data buf~er" of, typically, 256 words, then data can be transferred to and ~rom a ~pecific peripheral device at the comparatively low rate of the device; however, when the data buf~er is f~ll, data can be transferred to the Main System at the highest rate allowed by the memory speed o~ the Main Memory, which is at a fast rate.
qhe LCP Base Module, which houses up to eight LC~'s, operates in conjunction with the IOT to establish connection to and to initiate operation of a particular LCP. The LCP
~ase ~odule also supplies the timing signals, the maintenance logic, the power supply and cooling which is ~upportive of each group o~ indi~idual LCP's.
The IOT is that portion of the central processing u~it which~ upon receipt ofan I/O Descriptor, works in conjunction with the LCP Base Module to establish connec-tion to a particular LCP in the channel specified by the Initiate I/O
Instruction. The IOT translates the I/O Descriptor to a form (Command~Descr~ptor~ recogni2able to the LCP, and, when connection is , ~ 37 . . .

~ ) established, pass~s the ~ranslated de~cri~tor ~ tn~ ~r after which data transmission may begin. During the time that th~ data is being transferred between the LCP and the Main System~ then th~ IOT, UpOTl demand from th~ LCP, requests memory accesses, addresses memory, then modifies and compares the data addresses. Further9 the IOT controls the routing of data between the s~lected LCP and the Main System, and it performs translations (ASCII/EBCDIC) of the data if so required. Upon completion o~ an operation, the IOT accepts R/D (Result Descriptor) information from the LCP, and then ~tores the Result Descriptor in a predetermined location.
; The LCP s~stem con~iguration allows up to 68 I/O
channels. In the I/O Control Subsystem there ~ay be two CC!s tCentral Controls~ with eight I/O Controllers each for a total of only 16 channels.
In the LCP subsystem however there may exigt up to eight hCP Base Modules per single IOT. Each Base Module may service and carry up to eight LCP's. Thus, one IOT may serve as many as 64 LCP's. ~ Multiplex Adapter may be used ~o provide the e~fect o "two" IOTs connected to common LCP Base Modules. This con figuration may ~e used to improve I~O band pass to the Main Memory.
The entire ItO System has channel addresses which must be ` unique in themselves. Access to Main Memory is shared by the IOT, the Central Control and also the Processor.
In FIG. lA ~here is seen an overall system diagram showing the dual categories o I/O Subsystems. The first I/O Subsystem is made o Central Control 12 which supports I~O Controls 13a and 13b which connect respectively to peripheral devices 14a and 14b. This first I/O Subsystem ~using Central Control) is connected to the Main System 10 by means of interconnectlng bu~ 11.
. .

~ 38 _ : , ~; : .
...... ~ . .. . ..

- -i2~
.

The Main System 10 is shown comprising a ~lain ~lemory 10 , the Central Processor 10 , the ~lemory Control 10C, and the Input-Output Translator lOt~ A PCC (Peripheral Control Cabinet) interface 10i connects via bus 5 to a Peripheral Control Cabinet 6 which houses the Central Control and t~e I/O Control units o~ the ~irst I/O Subsystem~
The Input-Output Tr~nslator 10t Of the ~ain System, FIG. lA, forms a second I/O Subsystem through the use of cabinets shown as LCP cabinet numbers O, 1, 2, designated as 160, 161, 162. Each of the LCP cab`inets supports three LCP
~ase Modules, 0-8; for example9 base cabinet 160 carries Lase ~odules20Q, 201, 202; while LCP cabinet 161 supports LCP Base Modules-203, 204, and 205; likewise, LCP cabinet 162 supports I.CP Base Module 206 and 207. Each of the indi~idual LCP Base Modules is connected to the IOT 10t by : means of message level interface cables (MLI) 15, each of which is made up of 25 lines.
Re~erring to FIG. 2,a typical LCP base Module 2o is shown in greater detail The Base Module 200 is composed of eight Line Control Processors (LCPIs) 2000 through 20o7, in addition to ~ common Distribution Card 200d~ a common Maintenance Card 200m and a common Termination Card 200t. The Distribution Card 200d connects to one set o~ the messa~e leYel inter~ace cables 15 Which connect to the IOT 10t (also see FIG. 5E~ .

Each individual Line Control Processor is seen connected `~ ` by output lines to a particular peripheral devic~, ~herein~
as seen in FIG. 2 the LCP's 2000 through ~007 rsspectively co~ect to peripheral de~ices 50, 51, 52, 53, 54, 55, 55, 57.
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While each LCP of the Base ~lodul~ may be slightly different in certain aspects in order to accor~odate th~
idiosyncrasies of each particular peripheral device which - - the LGP handles, each LCP is of basically the same design and functional capability. With reference to FIG. 2, a *ypical example of each LCY i9 seen in the LCP 20o6 which is seen ha~ing a System Interface 21Si 9 a Device Interface 22di and ha~ing a Word Buffer 2506 which is typically capable of holding 256 words.
Referring to FIG. 3 there is seen a more de~ailed bloc~`
diagram of the ~ain System as it r01ates to the I/O LCP
- Sub~ystems. The Main System 10 has a Main ~lemor~ 10 in ~hich ~here is a reser~e portion lOmi for I/O Descriptors and a~other reser~re section IO for Result Descriptors.
In addition the Main Memory 10m has another reserve portion lOnC for storage of cha~nel numbers. The I/O Descriptors, Result Descriptors, and Channel Numbers are in~ormation used by the Syste~ for control and for recognition of the status of operations. These will be described in detail hereinafter.
T~e Processor 10 has a local register 10 r which is useful for storing information for the IOT. The I~put-Output Translator 10t holds a ch~nnel scratchpad memory 10 s-The local register 10 r of the Proeessor lOp is used for s~oring the beginning (A~ and the ending (B) addresses ... .
of the appropriate I~O Descriptor.~In the case of the first I/O
Subsystem using a Central Control~ ~IG~lA, the I~O C causes these addresses to be trans~erred into a temporary storage location called channel scratchpad memory or channel address memoryl. In the case of the second Subsystem using the IOT, the IOT

- 40 _ accesses the A and B addres~es directly from t~e memory address lines leading to the local register 10pr f the Processor. The channel scratchpad memorylOps for all 6~ LCP's i~ contained in the IOT. ~he channel scratchpad memories will also contain the required channel n~mbers.
~ith reference to ~IG~ 4A and the transfer of information as between the Main System 10 and a t~pical LCP 2000,a brief look at these information words and their functions wil~ indicate the nature of the operating relationship.
Command Descri~or 1 IG. 4A):
The Command Descriptor ~C/D) is a modified form of the I/O Descriptor. The I/O Descriptor is the information residing in Main Memory lOm, FIG. 1, which provides data and information as to the type o~ Input-Output operation to be accomplished. The modification of the I/O Descriptor is accomplished by the IOT 10t (Input-Output Translator, FIG. 13 which receives the I/O Descriptor from the System Memory lOm, retains a portion of the instruction, and then transmits the applïca~le portion to the LCP 20 as a Command Descriptor.
The Command Descriptor is a ~7-bit word, A, B, C, D, (FIG. 4B) consisting of an OP code digit (A), variant dig ts - 1 (B), 2 (C~, and 3 (D), and a parity bit. ~wever, the LCP 200 makes use of only the OP code digit and variant digit 1 for instructional purposes. ~ariant digits 2 and 3 are always equal to 0. The OP code digit (A) defines the basic operation to be performed by the LCP 20 , and the ~ariant digit 1 (B) specifies modifications of the basic operation. No memory addresc information is sent to the LCP;

~* ~ - 41 -_ ~ ~ ` 3 the System ~lemory address functions are accomplis~ed by the IOT lOt. FIG. 4B contains the Col~nand Descriptor codes ~or all operations that can be per~ormed by the LCP. These operations include: Write, Read? Write Flip Read, Test7 Test Enable, Conditional Cancell and Echo. These operations will be later described hereinafterO
Descriptor Link (FIG. 4~):
The Descriptor Link (D/L) consists of two 16-bit information words accornpanied by a longitudinal parity ~-ord (LPW). The Descriptor Link is exchanged between the IOT lOt, (FIG. 1) and a LCP, as LCP 2 000 - at specif ic times during com~unication between the two units. Ihe content of the De~criptor Link is shown in the following tableO The data bits which are not listed are reserved for future use.
TABLE IV :_ Descriptor LinX (Also see FIG . SD) Data Bit Desig~ation A8 Inhibit Access to system memory.
A2 ASCII Translation required.
. C~ Lase Module Address: 4 bit.
Cl Base ~lodule ~ddress: 2 bit.
D8 Base Module ~ddress: 1 bit.
~4 LCP address: 4 bit.
D2 LCP addr~ss: 2 bit.
Dl LCP address: 1 bit.
25 Data (Intelli~ence)_(FIG. 4 ):
These are the bidirectional communication lines for transfer ~- of data from the System 10 over to the LCP -such as 2000 for e~entual transfer to a peripheral unit such as 50; or Qtherwise for transfer of data from the peripheral unit 50 o~er 30 to the LCP 20 0 and thence to the System 10 for storage in ; .
.

, ~ 3~

Memor~ lOm. In FIGS. 1 ~ld 3, the3e chæ~nel3 would b~ the message level interfaoe (~LI) 15. Data transmiss-on between the System 10 ~nd the LCP 20 i~ in the for~t of words ~Table II~ ~cept ~or certain transmissions l~/hich a~e limited to a slng~e character or for txansmissions ending in an odd number of characters. Each "data word" is composed of two 7-bit ASCII characters and a single parity bit. Data bits A8 and C8 are not used, (Table II).
- It should be noted in regard to the Command Descriptor, that after receipt of a Command Descriptor, but prior to e~ecution of an operation, the LCP 20 receives the Descriptor L~k from the IOT lQt and ~stores it in th0 LCP buf~er 25 (FIG. 2). When the LCP 20 disconnects from the System 10, then recon~ect~ for further communication, the Descriptor Link is returned to the IOT 10t to ideilti~y the LCP and the operation in progr~ss.
t Re$ult Descri~tor_(FIG. 4A):
A Result Descriptor is generated by the LCP 2000 ænd ~orwarded to the System 107 after the instruction contained ~' 20 in a Command Descriptor (C/D) is executed, or when an error ~ occurs during receipt of a Comman~d Descriptor or a Descriptor `' LiDk The Result Descriptor is sent to the System LO by the ~ LCP 7 in a 16-bit word format, with a parity bit FIG. 4C
``~ sho~s the 16-bit format for ~ Result Descriptor, wherein ~ 25 digit~ A, B, C~ D will each have 4-bits.
. , .
Lon~___dinal Parity Word (FIG. 4A):
~he Longitudinal Parity ~ord (LPW~ is a 15-bit word representing the-longitudinal parity of each transmis~ion between the Syst~m 1~ and the LCP 2000. An LPW is accumulated in both the IOT 10t and the LCP 200o during a transfer of information between the two units. An LPW
register is provided in the LCP 2000 wherein accumulation of the LPW by the LCP 2000 consists o~ appl,ying each word being transferred to the input of,the LPW register and performing a binary add operation without carry (excLusive OR ~unction). Then at the end of a data transfer, the e~clusive OR function is again performed between LPW's of the- sending and the rec.eiving tmit. If no errors have occ~rred, both LPW's will be identical, and the resultant value in the LPW register will be "all O's".
Input-Output Iranslator_ ~IOT) (~IG. 5C):
The IOT 10t translates the system I/O Descriptors into ~ the appropriate operational messages releYant to each LCP.
- 15 In,return the result messages from the LCP in the form of - Result Descriptors are.not translated by the IOT, but are ` stored directly into Memory 10 at~lOmr as transmitted ~y the LCPs.
The IOT performs all the information transfers between the `~ LCP19 and the Main Memory 10m necessary to support the input-output capability of the second I/O LCP Sub~ystem.
5he I/O Descriptors, which are sent to the IOT from ~emory lOm,are shown in FIG. 5A. Section lA o~ this figure ~ shows the descriptors used by the IOT to generate command .~ messages C/M for the LCP~ These can also be re~erred to as ~ 25 Command Descriptors C/D. Section lB indicates descriptors .~ used by the IOT. Operations 40 through 58 are translated into LCP OP codes and sent to the LCP's in ."message" format.
The "L" digits in the variant ~ield carry in~ormat~on used in the variant digits (B, C, and ~) of the descriptor .
~ 44 -~9~ 2$~

- informa~ion sent to the LCP's. ~le S-digjt i~ us~d by the IOT as sho~n by the note of section lA of FIG~ 5A~
Each operation shown iIl FIG. 5A has two OP codes; the difference is in the nu~ber of addr~sses used by the I,CP~
The first digit of the OP code desig-na-tes the n~lber of addresses required. For e.Y~mples a value of 4 desi~lates t~o-address operation (e~cept "test" which ha4 none); a - value of 5 for the first digit of t~e OP c~de designates ~hree address operation~ The second digit of the OP code is mapped i~to the actual ~P codes sent to tlle LCP ~ s as the digit.
FIG. ~B ~shows the data ~ield boundaries of operations going in -the fo~ard direction and in the bac~;ward direction~
~orward = System to LCP).
FIG~ 5A also sho-ws the four types of standard operational messages us~d fo~ controlling -the LCP's: these are 1. Read 2. Write ~ 3.- Test `, 20 4. ~cho ! The ~pecific descrip-tor information is obtained ln the ! ~orm o~ ~asiants which accompany -these OP code3. 1'Read" and "~rite~ ~equire system memory access. AIl operations whi~h do not tra~s~er data are considered "Test". Thus~ a "Test"
is defined as an operation which results in the IOT recei~ing result infoI~ation only~ "~cho" is a con*iclence test oper~tion which oauses the LCP to accept a buffer load of in~o~mation f~om *he S~stem 10 and then return it to the 5yste~ 10 for cheok-out.

~ .

:
All communicatio.ns between the Main System lO and the LCP is over a stanclard message level interface 15 (~LI).
This communication bet~lten the -iOT and the various LCP's is accomplished by a standard flGw discipline which is common to all LCP's.
In FIG. 5C the IOT lOt receives I~O Descriptors frorn the Processor 10 . ~he IOT then connects via Distribution Unit 200d to the reques-ted LCP channel and sends -the translated descriptor information (Command Descrip+or C/D) in a message format which indicates the LCP's task~ The IOT then :
becomes LCP "stat~s driven". This means that the IOT responds to the various LCP s,tates (including memory requirements) as indicated via the controllines between the LCP and the IOT
FIG. 4A. The IOT manages the transfer of information between Main Memory and the LCP's. The LCP's memory requirementS
" drive the IOT for all data -transfers except that of initiation.
Either the IOT or the LCP can initiate a connection to . Main Memory 10~. The IOT initiates a Main Memory connection ~0 to an LCP (and its associated peripheral) by per~orming an ! algorithm which is called a "Poll Test". On the other hand, the LCP initiates a connection to IOT and Main Memory ~y an algorithm called a "Poll Request". Once the LCP is connected, it indicates its status -via the control lines of ~IG. 4A. An LCP which i9 initiating a "Poll Reques-t" must compete with the other LCP's in the system; a connection to Main M~ory 10m is granted on a priority basis which will be described ~ hereinafter. Dhlring an operation, the IQT 10t may disconnect ;` from one ICP in order to service another LCP.

., .

~ 6 -. .

`) The message transmissions betweell the IOT and the LCP
i~olve data and control messages whlch are transmitted 16~bit3 at a time along with a vertical odd parity bit.
Following the last message, a 16-bitlongitudirlal odd parity 5 word (LPW) is transmitted accompanied by a vertical odd parity bit. Parity is checked by botn the IOT and th~ L~P.
If a parity error is detected by the LCPy then the LCP
report~ this in its result information transmission (Result Descriptor) and halts the op~ration. If the IOT detects a parity error, it i9 inserted in the L~P ~esult Descriptor.
The Input-Output Translator 10t (IOT) consists of four m~jor func-tional sections, each concerned with one particular aspect of i~lp~t-OUtpUt o~eration. These functional sections are shown in ~IG. 5C. Furthera the operating relationships between the ~OT and the Main System (Processor and Main ~emory3 and also the LCP and the peripheral device, are also ~hown.
Referring to ~IG. 5C, the Input-Output Translator 10t co~municates ~-ith the Processor 10 and the Main Memory lOmO
~he IOT lOt also communicates with a selected LCP as Line Contxol Processor 2000 and the peripheral device 50. A series of control lines in FIG. 5C are shown from the Processor 10 to ; the Initi~tion Module 10t , the CoImection Module lOt~, the ~ata Trans~er Module lOtC and the Reconnection Module lO~d.
Initiation Module-.
The Initiation Module lOta accepts the descriptor in~ormation, including the addresses, from the ~rocessor 10, a~d then translates the descriptor OP code and assembles th~
information into a form usable by ths LCP ~oa~ The A and the ~ 47 -~ . . . . .

2~

B addresse~ of the descriptor are stored in the IOT
scratchpad memory 10 , FIG. 3, which has locations rese~vec for each designated channel; the rest of the descriptor information i~ assembled in a re~ister (as shown in FIGo 5~) for subsequent transmission to the LCP 2000. Once -the information is assembled in thîs "descriptor info~mation regl~ter" and the addresses are stored, then the contents of the fir t rsgister are shifted to a second identic~l regi-ster. ~n this manner, the first register can be cleared and the Initiation Module lOta is thereby ~reed to aooept a ~econd descriptor.
. The infor~ation contained in the descriptor register o~ FIG. 5D consists of a number of items:
~, (a) LCP OP CODE s these are four mutually exclusive ~ bits, w~ich are translated by the IOT from the ! I/O Descriptor OP code; they indic~te to the LCP
the type of operation that is to be commenced.
(b) LCP Variants : these are three digits which are ~- used to pass supplementary information to the ~CP concerning the operation that is to be i commenced.
! (c~ IOT Digit : this digit s~ecifies if data transfers j are to be inhibited ~nd whether or not dzta is to be translated.
; 25 ~d~ Backwards Fla~ : when on, thi~ fIag bit indicates j that a reverse operation is to occur.
¦ (e) LCP Address : this is.decoded from the "BF"
~channel numDer) of the procestor Initizte I/O
! in~ruction; this field contains three bits which ` 3, _ 48 -~ ~ .

~ . . .. ~ . .. .. ..

%

specify one o:E the eight LCP Base Modul~s, and the other three bits which are used in corn~inati~n to select a par-ticular LCP in the designated Ba.se - -Module.
(f) ~ Ad~ress : this is a six-digit C-Address field (file address) o~ the I/O Descrip-tor.
The combination of the IOT digit, the backwards ~lag, ~nd -the LCP address constitute the Descriptor Link (D/B~ ~hich i~ ~sed by the ~CP to re-establish connection to the System following a previous disconnection. When the Processor si~nals ths lOT that the entire I/O Descriptor has been sent, the IOT di.scon~ects ~rom the Processor, and the Xnitiation Moduls lOta passes control to the Connection M~dule l~b.
; Connectlon Module `, 15 T~e ~,onnection ~lodule lOtb o~ FIG. 5C has the purpose of e~tablishing a com~unication path betwee~ a designated LC~
~¦ such as LCP 2000, and the Inp~lt-Outpub TransLator lOt. The ~; Gonnection ~lodule lO~b decodes the channel number which `I appears in the Proces30r Initiate Instruction~ and, with the ~ 20 decoded ~alue, selects a communication path to the LCP Base ! Module such as 200, FIG. lA,in which the desired LCP is i located. The~ Connection ~odule lOtb then sends the LCP
¦ address ~o the selected LCP ~ase Module, and then signals ', the Base Module, such as 200 t to begin a "Poll Test~.
:' 25 Poll Test:
The "Poll Test" is an algorithm used by the LCP Base Module to establish connection between the Ba.se Module and ! a particular LCP; the~Poll Test algorithm is a connection ' which is initiated by the IOT (as contrasted with an .
.

`.

! `) !

algorith~ called "poll request" w~ich i5 a connection initiated by the LCP). Once the connection between the LCP
Base Module and the specific LCP is ~stablished9 the B~se Module, SUC}l as 200` FXGS. lA a~d 2, becomes transparent to data transfers-between the LCP and the IOTo The "Poll Testn algorithm also checks for priority, trans~ission errors, ` and busy condition~, any one o~ which, if detected, could abort the connection attempt.
. If the connection attempt i5 success~ul, the specific .~ 10 ICP remains connected to the IOT 10t until t~e connecti~n is terminated by the IOT. ~le LCP ~ase Module ta~es no further role in the communications between the chosen LCP and the IOT.
In the course of the attempted connection, certain conditions may be detected whic~.will stop or abort the connecti~n attempt~ with the result that the existing condition is r~ported in the IOT ResultJDescriptor. The following are the types of conditions detected and reported:
(a) -The channel addressed does not containan LCP or . 20 the ~CP in the channel is off line.
(b) The LCP in the particular ch nnel addressed is busy", (that is, the LCP status is not 2 or 3j the use of ~status counts" will be described hereinafter~.
` (c) The port is busy, that is, some other LCP in that ; ~ase Module is presently connected to the System 10.
~d) The LCP address has i~..it a parity error.
When the IOT and Base.M~le Distribution Control ~eans ~ uses the "Poll Test" or.connection to a particular LCP, then if the Poll ~est results . .
.
-- 50 ~ .

: `-2~

in connection to that L~P, the IOT 10t will transmit the Descriptor Link (D/L), the ICP OP code and variants, and the C address to the LCP selected. After receivin~ this information, the LCP signals the IOT 10t that it is either going to disconnect, or that it is now prepared to begin to transfer data~ Typi.cally, a "Write" operation (dat~ from M~in Memory lO to the peripheral device~ such as peripheral 50~ causes the LCP selected to request a "data transfer"; on - the other hand a "Read" operation typically results in a disconnection.
If a data transfer is requested, the Connection Module lOtb ~asses control over to the Data Transfer Module 10t .
If the LCP 2000 disconnected, then communication between the LCP 200~ and the IOT 10t i5 te~ninated untîl the LCP
requests a re-est~blishment of communicatiosl via the .~ . . .
Reconnection ~odule lOtd.
Data Transfer ~odule:
In FIG. 5C the Data Transfer Module 10t is used by the IOr 10t to control and to direct the flow of data between a connected LCP 2000 and the M~in Memory lOm. The LCP may be in a connected state as a direct res~'t of the actions of the Connection Module lOtb~ or a~ a result of the actions of ~he Reconnection Module lOtd;.in either case the ~peratio~
~ of the Data Transfer Module 10t , is the same~ When control i 25 is passed over to the Data Transfer Module lOtC, the A and B
addresses of the descriptor are retrieved fromIOT scratchpad m~mory 10 s of ~IG. 3, where they had been stored by either the Initiation ~odule lOta~ or by the Data Transfer Modul~ lOtc of FIG. 5C, at the end of a prior data transfer operation.

, A memory a.ccess request i~ made and the A address is transferred from the IOT 10t o~er to the Processor memory address register lOpam in the Main System 10, ~IG. 3.
Assuming that a :~Write'! operat on is in progress, in FIG.
5C, the data from the memory location specified by the A
address is bussed via B to the IOT Data~Transfer Module 10t Once in the module~ the data is translated (if specified by . the descriptor), and used to generate longitudinal parity, and ; then-is gatsd ~ia bus B to the selected LCP such as LCP 2000 ~
g accompanied by a Ytrobe pulse. When the LCP ~0 receives the data9 it acknowledges the reception by returning a strobe pulRe ~acX to t~ IOT lOt.
While the data transfer from Memory 10 o~er to the `~ LCP 2000 is occurring, the IOT 10t increments the A address ~nd compares it to the B address. A3 long as the A address is les~ than the B address, the reception of the acknowledged stro~e pulse from the LCP 2000 will cause another memory access to be requested and will allow the data trans~er sequence to continue.
When the ~CP buffer, such a~ 25Qo, FIG. 2, i~ Pilled with data from the Memor~ 10 , the LCP signals the IOT 10t that it is going to disconnect; the IOT 10t then restores . the incre~ented A addre~s to the IOT scratchpad me~ory 10 s' FIG. 3, after which it terminates the connection between the i 25 IOT and the LCP. Th~ LCP, such as LCP 2000, then begins . data transmission via B with it peripheral device 50; the IOT 10t is now free to establish connection to another LCP.
Upon transferring the contents of its data buffer 25 0 to the peripheral device 50, -the LCP 2000 requests a ;
. .

r~-establi:.hm~nt of the data path ~o ~IQin M~mory lOm. lh :~ re-establi~hment is handled by the LCP Base Module 200 and the IOT ReconIlection ~lodule lOtd.
~n ord~r ~o increase the overall r~te of input-output (I/O) acti~ity, the IOT 10t may contain, as an opti.on, an IOT ~ultiple~or. This multiplexor would ~nable the IOT to ~ervicean LCP during those memo~ cycles which w~uld otherwise be lost while the IOT was busy with some non-memo~ function.
R~connection ~lodule:
; 10 ~ An LCP, ~ch as 2000 ~ after having baen connectsd to tne IOT 10t and recei~ing the Command Descriptor (C/D) and *h~ Descriptor ~ink (D/L), then the LCP 2000 may disconnect from the ~y~tem in order to co~municate with its associated pe~ipheral device, stlch as d~Yice gO. Nowy if t~at LCP
15 subsequently requires access to ~emory 10 , ~t sends a request to th~ ~ase ~dule 200 An algorithm called the ~Poll Reques~" is the method by which the LCP Base Module (in re~ponse to the request of the LCP) attempts to connect the LCP back to the IOT lOt. The Base Modulë`~i-s~ri~t~on Cara~-contains hard wired logic to accomplish this. The purpose o~
the Reconnection Module lOtd is to acknowledge the "Poll Requ~st"
and to _e-establish a data path over to the IOT lOt.
The Reconnection Module lOtdr during the reconnection attempt, and working with-the Base Module, as 200, resolves any priority conflicts that may arise between various request-ing LCP I 5 When priority is resolved, the Reconnection Module establishes the data path ~rom the requesting LCP over to the Main Memory lOm.
Once the data path is re-established, th~ LCP returns the Descriptor Link over to the IOT lOt. (The Descriptor - 53 ~

Link was originally passed to the LCP 2000 during the original connection sequ~nce3. The, Base ~odule 200 takes no ~urther role in tha, Li~P-IOT co~unication. Following the transfar of the Descriptor Link, the ~ecG~lect~on Mo~ule lOtd passes control to the Data Transfer Module lOtC~, Th9 IOT 10t must have the ability to accept, store and to modify d~ta field addresses in order to transfer data to and from the correct memGFy locat:ions. Because Main ~emory 10m ~ay include up to, two-~illion digits ~addrec~ses O to l,9~9~999), and because the ~arious input-output devices ~ay address the Memory 10m directly, then the I/O descriptor data field addre,ses must be seven digits long. An I/O
descriptor data field address must be eithe,r MOD 2 or MOD 4 (modulus is abbreviated to MOD); no odd addresses are permitted.
Because Ddd addre~,sec, are not allowed9 the lea~t significant bit of the least significant digit i5 not required.
Furt~ermore, since the most signific~nt digit can be only a l" or a ~0", only one bit is required for the digit position.
With these facts,-, it is possible to construct a seven digit address using 24-bits. The fo~,at ~or the I/O descriptor data field address is shown in the ta~le V below.
TABLE V

~' G F E D C B A Digit Positior Bit ~ ~

I/O Ds~scriptor Data Field Address Note- ~ inflicates bit not used; must be zero ~ 54 -. ,'~ ~,,.

In the a~dress~ the ~igit G may be a one or a ~ero, ., .
digits B through F may be any decimal ~a~ue (O ~hrough 9), and digit A may be any even decimal ~alue (O through 8).
- As was indicated in FI(J. 3, the IOT 10t kas a scratchpad msmory 10 . This~is shown in greater detail in FIG. 5F.
The IOT contains 256 words of scratchpad memory, each word of which is 24-bi,t~ long. As seen in FIG. 5F,'the scratchpad memory is divided into five major areas. The areas marked A
and B are used to store the begin (A) and the end (B) addresses of the memnry data field; both of these addresses are 24-bits long. The areas marked EXRDW i and EXRDW 2 are u~ed to store e~ten~e~ result descriptors wherein each of 'these words are 16-bits long. The area marked ~temporary storage" is used to store flags indicative of error~ de-teoted , during IOT operation. When the ~esult Descriptor is ' a~sembled, the information from the temporary storage area is a~ded to any existing Result Descriptor information.
Each of the five major areas i~ subdi~ided into 64 individual locations, one for each channel.
, 20 The scratchpad locations are addres~ed by a combination i o~ eight bits which represent the Base Module number and -the ¦ ICP number~ the end address flag (ADDRESB)~ and the extended result descriptor flag (EXRDW 1~. The 3ix least significant bits of the scratchpad addre~s (Base Module ,, number and LCP number) are deri~ed from the BF portion of the Processor's Initiate Instruction (~FA = basa number, BFB = E&P number). The EXRDW 1 signal is gene~ated by the IOT 10t whene~er access i9 required to either the extended Result Descriptor word, or to the temporary storage area.

:' . `

~ 55 ~

6~
;.
,. .

ADD.~ESB i5 generat~d by the IOT ~ihe~lever access is required to a B address or to the second e~tended Result Descriptor area.
Ihe ~emory ele~ents of the scratchpad lOp5 consist o~
24 RAMs (256 x 1), organized in a 64 x ~ Y 24 array (64 ~, - channels, 4 words per channel, 24-bits per word). As seen in ~I~. 5G, the eight-bit ~ddress bus 9 Bad, goes to all RAMs, 600, 601 -.6024~ in the array9 as do~s the Write Enable line 68. Each ~ has one data input line and one da-ta output line; these indi~idual data lines are combined to make up the data input (RA~IIN) 7i and the data output -~RAMOUT) 700 busses respectively.
When the scratchpad address is applied to the array;
~nd the "Write Enable" is made acti~e, the data on the IOT
address bus is written into the R~Ms. In order to read from , ~he scratchpad~ the desired location must be speci~ied with - the scratchpad address and the "read enable" must be made active. The requested data is then transferred from the ~cra-tchpad to the IOT address bus.
Address Store:
During the execution of an Initiate I/O Instruction~
~he Processor 10 assembles the be~inning (A) and the ending (B~ addresses of the data field. T~e Processor then transfers ~, the complete A address from the Processor register lOpr to the IOT address bus. At the proper point of the IOT initiation " sequence 9 the IOT generate~ the a~propriate signals, then ' gates the Base Module and the L~P address bits to the scratchpad 10 5. Now, wi.th the channel~s scratchpad location ... .

~ - ~6 -~ .;,~ .~

addressed and with the 'lWrite Enable" active, the A address can be written into the sckatchpad~ Subsequently the Processor 10 places the end (B) addre~s on to the IOT
address b~s and again the I~?T generates ths proper control signals along with the Base Module and LCP address. This time, however, the IOT also generates ADDRESB, thus causing ~
the address on the bus to be written into the B address area of the scratc~pad (FIG. 5F~. The beginning and ending addresses of the data field have now been stored in the channel~s address memory scratchpad 10 5 . When the data transfer operation begins, these scratchpad locations ~ill be accessed by the Data Transfer Module lOtc (FIG. 5C~.
MAssa~e Level Interface:
As was previously described in referènce to FIG. 2, the LCP Base Module 2o is typical of the other Base Modules in _.
~ t~at each individual Base Module contains a Distribution ?~ Card 200d which services up to eight LCP's. In addition, j each LCP ~ase Module has a Maintenance Card such as 200m and ¦ a Termination Card 200t. -The Distribution Card ~or each LCP ~ase Module pro~ides an interface between the LCP Base Module and the Input-~utput Translator 10t of the MaiIl System 10. A~ seen in FIG.
2, the message level interface 15 provides a channal -to the IOT 10t from each LCP Base Module by means o~ ~5 lines. ..
These lines are shown in FIG. 5E. The fhnctions o~ each of - these individually identified lines are listed in tabl2 ~I
herein below: .

:`. 5~ -6~$~2 .~
, TABLE ~I _ _(~e-er to FIG. 5F al.so) , '` Si~nal Name De cri~tion ADDSE~ Addre~s Select. This signal 7 wh~n acti~e, indicates'that the I~T is connected to, or is attempt.ing to connect to, a specific LCP.
Once the co~nection is made, the LCP remains connected unti- the IOT drop~ ADDSEL.
AG~SIO Access ~ranted or Strobe I/O. If an LCP
is not connected, this signal indicates that the ~CPs request for reconneçtion has been ~ranted, and initiates the "Poll Request"
algorithm. If the LCP is connected, tkis ignal i9 the IOTI~ acknowledgement for ~ information recei~ed, or strobe for information .~ 15 transmitted~ . .
I TRM+MC Te~minate or'Master Clear. I~ no LCP's are ' connected~ this signal will cause all on-line LCP~q to clear~ If an LCP is connected, this ~l ignal ~il- terminate the çonnected LCP9 ~, 20 W PST LCP Strobe. If an LCP i9 connected, thi~
signal is the LCP's ack~owledgement ~or ~ information receiYed9 or the s~robe for .~ info~mation transmittedO This signal i5 ', al~o u~ed by the Distribution Card as an acknowledgement durlng Poll Test and Poll t Request.

. ' ~

. ~. ' ' ' .
. . . - 58 . ~ :

~ \
2~:

Si~nal_Name Descr ption - ~R+ST8 Emergency Request or LCP Sta~ls 8.
When activated by an uncolLnected ICP, this signal indicates that the LCP requires immediate access to the IOT. If activated by a connected LCP, this signal indicates that bit 8 of the LCP status is set.
IP~ST4 Interrup-t Request, Poll Test Parity Error, - or LCP Status 4. When acti~ated by an unconnected LCP~ this signal indicates that the LC~ requires access to memsry7 i.e., the LCP is requesting a reconnection. I~
acti~ated during a system-initiated connection sequence (Poll Test), this signal indicates ~ that a parity error was detected during the Poll Test. If acti~ated by a connected LCP, I IP~sT4 indicates -that bit 4 o~ the LCP
i status i~ set.
;j PB~ST2 Port Busy or LCP Status 2. When detected ~uring a Poll Test, this ~ignal indicates ` ~hat the LCP Base is~nbusy". If aotivated j~i by a connected LCP, PB~ST2 indicate~ that . j ~'~ bit 2 of ~he LCP status i9 ~et.
~- CS+STl Channel Select or LCP Statuq 1. When v 25 activatad by the IOT and transmitted to an LCP Base, this signal indicates "channel selecti', and that a connection or reconnection attempt has been initiated. If acti~ated by a connected L~P~ CS~STl indicates ;~ 30 that bit 1 o~ tha LCP status is set.

~ 59 -~ .
'', ..

~Y~ Descripti _ PARITY Parity. Thi5 bidirectional line carri~s the proper (odd) parity for the information on the 16 data l:inesl DA~ALYn Data Lines (x=A, B, C, or D; n=l, 27 4, or ~)~ ~n the unconnected state, these 16 bidirectional lines are used for addressing and priority resolution in connection or - reconnection attempts. In the connected state~ these lines are used for the transfer o data between the IOT and the LCP.
The message level inter~ace 15 (ML~) ~ihick consists of 25 signal lines connecting the Distributivn Card as 200d~ of a partieular LCP Base Module as 200, ~o the IOT 10t provides assurance that the signal discipline presented to the IOT is ~¦ a ~tandard one regardless of the ~ariations of logic and ~¦ opera*ion found in the different types of LCP's. It will be '~ no*ed that some o~ the ~I signal lines 15 shown in FIG~ 5E
~ are bidirectional 9 and are assigned multiple ~unctions, .~
dep~nding on the ~ource of the ~ig~al and the state ~connected ; or disconnected) of the LCP.
,~ ~ . Th9 Distribution Card 200d for a gi~en LCP Base Module i ~ used to provide a part o~ the Message Level Interface between the IOT and the indiYidual LCP~s within the Base Modul~. The Distribution Card also works in conjunction with the IOT Connection Module lOtb to establish a data path to a specified LCP (Poll Test), and, upon request by an LCP, works with the IOT Reconnection ~odule lOtd to establish path from that particular LCP to the IOT (Poll Request)~.
~j .

~ 60 -.~ , , ,."~.

j,.--.~ ~

LCP_Status CoUI~ts_ During the time a particular LCP is connected, it ~ollows a standard communication procedure with the IOT. Although the sequence o4 events ~ollowed in the communication - 5 proc~d~re may not be identical ~or all LCP's, t~e events occurring in anr one point in the sequence will ~e identical.
The steps in the sequence~ which are numbered O through 15, are called "Status Counts" and are transmitted to the IOT.
The IOT exa~inas the "Status Counts" each time it receives a strobe pulse from the LCP and~ based upon that status count, takes appropriate action. More detail in the sequence and use of status countC will be pro~ided hereinafter. FIG. 6A
i~ a diagram showing the various status c~unts and the logic M ow which they involve. Detailed explanation of this logic and the statlls counts involved will be provided hereinafter.
LCP Base Module Backplane:
j A local common backplane is proYlded in each of the LCP
3 ~a~e Modules 200, 201, 202 3 etc. Each backplane cnnnects to all the eight LCP's in the Base Module. The backplane is constructed so that all signal lines are bussed the length ~ of the backplane, thus making each line available to all : 3 LCP~ in that Base Module. From the indi~idual position of a ~ingle LCP7 these backplane lines ~all into two general types:
~a) tho~e going to the Distribution Card and on to the IOT;
and ~b) those goin~ to the Maintenance and Termination Cards.
With the exception of the variou~ clock and voltage lines, those lines going to the Maintenance Card, (such as for example, 200m of ~IG. 2) are used for local or of~-line maintenance functions.
.`~' ' . ' ~ ..

6~

Of those lines ~hich go to the Distribution Card, and on to the IOT, some, such as the data and the parity lines, - must be gated to indi~idual LCPs. This gating ls enabled - only wherl the LCP i9 in the '9cvnnected" stato; when the LCP
disconnects, the gating is disabled. The LCP i~ in a "conneoted" ~tate when the LCP can transfer data between *he IOT and itself. The "disconnected" state of an LCP is where the LCP is disconnected from the IOT, but is now able : to transfer data bet.ween itself and its peripheral unit.In addition to the gated lines, there are some lines which are dedica~ed to each individual.LCP, for example, the line which ~oes ~rom the Distribution Card to only one LCP.
ThoS9 lines, which require no gating) are used for signals such as the T-CP request for reconnection or the LCP address 1$ lines.
During the time an LCP is connected to the IOT, that : LCP has the exclusi~e access to the Base ~odule 8ackplane.
It is during this "connected" time that the IOT-LCP data transfer occurs. Upon cessation of the data transfer~, the LCP disconnects from both the IOT and the Base Module ~ackplane, thus freeing them for u~e by other LCP's in the system. Once disconnected, the LCP is frse to communicate, via the ~rontplane, with it~ associated peripheral device, ~uch as deYice 50. When a dlsGonnected LCP requires that the connection to th~ IO~ be ra-established, that LCP sends a request signal, via one of its dedicated backplane lines, to the Dî~tribution Card, such as 200d~ Reception of the L~P request causes the Distribution Card to begin the "Poll Request" algorithm and to initiate the IOT Reconnection 3 Module~ lOtd, FIG. 5C.

: ' Line Con~rol Processor:
An-LCP, Line~Control Proce sor, i5 a device which is used as an interface ~nit between a specific peripheral device ~nd the Main System. The LCPs are made in a variety o~ types, each designed to operate with a specific type of peripheral device. Since peripheral devices are different in their operational characteristics, th~ LCP is de~ised to handle t control and be particularly adaptable to its own ~pecl~ic peripheral device. However, there are certain general characteristics o~ the LCP interface unit which e~tablish a com~on characteristic for all LCPs. Basically, the common characteristics of each 7CP invol~e3 the ability to transform ~erial data to parallel data or to transform parallel data to serial data; to transform format from 1$ character-to-word format, or to tran~fo~m from word-to-character format; to recognize and take appropriate action in r~ponse to certain standard control characters or signals.
~ ~ generalized block diagram of a Line Control Processor ¦~ is ~hown in FIG. 6B~ which also indicates the relationship 1 20 to Distribution Card Unit 200d and IOT ]t- If the LCP is asYumed to be in the ~Iconnected~ state, and that a "write"
I operati~n has been initiated, then data from the IOT 10t ¦ enters the LCP through the backplane recei~ers 23r. ~hen the i Multiplexor Z4xl is used to select the "data source" for the operation, which in this case i9 th~ IOT 10~.
~he output of Multiplexor 24Xl is bussed to bot~ the LPW (longitudinal parity word) circuit~y 24W ~nd also to the Multiplexor 24~2, which gate~ the data from ~ultiplexo~ 24 1 . .

., ' .

into the data buffer 25 . The LCP continues to receive data from the I~T 10t until the data buffer 25 0 is filled.
In the period that the LCP is receiving data, the LPW
circuitry 24 is gonerating-the LPW sw~; -then at the end of the transmission, the IOT 10t sends a longitudinal parity word (LPW~ w~ich~ if there were no errors in the tra~s~ission, clears the LPW circuitry 24w. If the circuitry 24W does not clear, then an error is indicated~
When the data buffer 25 is filled9 the LCP disconnects from the Main System (IOT) by ~isabLing its backplane transmitter drivers 23X and backplane receivers 23r; the LCP
then establi~es a data path to the peripheral device~ such a9 50, by enabling its frontplane transmitter drivers 28 ànd frontplane receivers 28r. Once thi~ path is established~ the LCP uses Multiplexor 27X to sele¢t data (translated or untr~nslated) fro~ the data buffer 2500 to be transmitted to the peripheral de~ice 50- The transmis~ion continues untiL
the data buffer 2500iS empty, at ~hich time the LCP requests a ~reconnection" (to the IOT~, either to tore a Result ~0 Descriptor or to request more data.
; If a "read" operation is in progress and the LCP is ;¦ disconnected from the Main System (IOT), data from the peripheral deYice 50 enters the LCP Yia the frontplane .
~ receiver Z8r. The output of the receiver 28r is bussed to :i. 25 Multiplexor 24Xl, which now 3elects the peripheral de~ice 50 `` t (through frontplane receiver 28r) as the "data source'l- The output of Multiplexor 24 1 bypasses the LPW circuitry 24~
~nd goes on to Multiplexor 24X2, which selects ~ultiplexor `~ 24Xl as the input to the data buffer 2500, When the da'a :` ~
, ~

~ "i. ' ' ..

- "` `

buffer 250oiS filled, the frontplar~s recei~ers 28r and the frontplane dri~ers 28 are disabled, then the LCP reconnects to the IOT lOt, and the bac~plane receivers 23 and bac~plane driYers 23X ~re enabled.
The LCP now b~gins transmission (to the Main System 10) o~ the data from the data buffer 25 , through the Multiple~or 27X and dri~er 23~, over to th0 IOT lOt. During this transmission, the output of Multiplexor 27~ also goes through the Multiplexor 24Xl o~er to the LPW circuit 2~ . ~hen the data buffer 2500 becomes emptied, the LCP sends a signal to tha IOT 10t indicating that the longitudinal parity word9 ~PW, is coming, after which it then gates the final LPW
qum through Multiplexor 27 and dri~er 23X over ~o the IOT 10t After the transmission of the longitudinal parity word (LPW), the LCP may either discon-nect from the Main System (IOT) in order to recei~e additional data from the peripheral de~iee 50, or, if there is no further data, the LCP may store a Result Descriptor and go on to an "idle" state.
In the abo~e described operations, the informationQl data could have been transferred between the LCP and the peripheral de~ice in the fo~m of bits, characters, or words, depending on the type of peripheral device in~ol~ed. ~he i method Or data transmission is typically controlled by the type of peripheral device used.
Typlcally, the informational data is transferred between the LCP and the IOT 10~ as "words", with some instances Gf character transfers, as for example 9 the first or the last character of a transmission. These data tran~fers be-twe0n I the IOT 10t and the LCP of ~IG. 6B are controlled by the :;
- 6~ _ .

.
6~

exchange of strobe pulses, an-l the reco~lition by th~ IOT 10t of the LCP "status counts", to be describ~d hereinaf`ter.
As pre~iously introduced in cor~ection with FIG. 6A, the status count of an LCP provides sta~dardiz~d inforrDation which is transmitted to the IOT 10~ and which permits the IOT
to take the next appropriate action based on the status count information.
During the time an LCP is "connected" to the Main System, it follows a standard communication procedure with the IOT lOt. Even though the sequence of events followed in t~e communication procedures may not be identical for 811 LCPS, tha particular svents which occur at any one point in the sequence of com~unication procedur~ are all similar.
The steps in the communication sequencel n~mbered O through lg~ are called i'status countsn and designated "STC'1. These status counts are transmitted to the IOT 10t which examines ~ the .status count (STC) each time it receives a strobe pulse j from the LCP, and~ based upon that status count~ the IOT
~¦ can take appropriate action.
Referring to FIG. 6A and the following table, it will be seen that each status count has a particular ~unction and fhrther, depending on the type of LCP an~ Descripto~
r involved, the status count will ha~e different exits. The '~ following table ~II briefly describes the YariOUS LCP
status counts:

Status Colmt ~
STC-O Ma~ter Clear STC=l Disconnect. The LCP is communicating with it's peripheral de~ice.
, ' , ' `~
-STC_2 Not ~eady. The LCP i5 idle. The periph~ral device is n~t ready. The - LCP c~n receive descriptor information ~ from the System.
STC=3 Ready. The LCP is idle. The peripheral - de~ice is ready. ~le LCP can re-~eive ~ . descriptor information from the System.
- 10 S~C=4 Read. The LCP transmits data from its buffer to the S~Istem.
STC-5 Send Descriptor Link. The LCP sends the - Desoriptor Link to the IOT in order to re-establish connection, 1~ STC=6. -Receive Descri~tor Link. The LCP recei~es the Descriptor Link from the IOT during ~he IOT ~connection" sequence.
STC=7 Result Descriptor. The LCP transmits its Result Descriptor to ths IOT.
STC-8 ~rite. The LCP receives data from ths System 4 -STC=9 Encoded Status. One character tran~mitted;
~CP sets Dl bit (~IG. 4C Result De~criptor) as a flag to the IOT. The IOT decrements 25 . ~he address by 2.
¦ STC=IO ~ri~e One More Word. The LCP data buf~er ca~ hold only one more word.
STC=ll I/O Descriptor ~PW. The ~CP receives and checks the LPW for the I/O Descr-iptor reoeived in STC-2 or STC-3 The I/O Descriptor, after being translated by the IO~, then be-come~ known as the Command Descriptor.

æ~%
!

TA~IE VII
Status Count ~
STC=12 Break. ~lere is no more data to be transfePred. The ~P~ i5 tranemitted and cheGked.
STC=13 Break Enable. Data transfer has been halted; th~ LCP is requesting a return *o STC=8 (Write) or to STC=4 (Read).
STC_14 Character Transfer The last transmission consisted of a character instead of a word.
STC=15 Result ~escriptor LPW. The LCP sends the LPW for the Result Descriptor to the IOT;
Referring to ~IG. 5~, the Processor 10 starts the chain of input-output operations by the execution of an Initiate '~ I/O ,nst~uction. In this situation, the Processor passes i certain lnformation, including the channel number of the ! de~ired LCP over to the IOT Initiation Module lOta of FIG. 5C.
The channel number is decoded to determine the Base Module number and the address of the LCP, w~ich ar~ then passed over to the Connection Module lOtb. The Connection Module then ~elects the proper LCP Base Module and send~ a signal (channel select) to the appropriate Distribution Card, as 200d~ for that Base ModuIe, as 200, requesting that a connection attempt be made. The a~o~e described operation i3 called a ~Poll Test~ and is a means for the Uain System to see~ connAction to an LCP; it is 3 further, a method by which the Distribution Card 20 d~ in response to the c~nnection request, also attempts to connect to a specific LCP.

. . .
_ 68 .

~ 3~ ~

Following t.he tr~nsmission of a '1Channel Select", the IOT 10t sends the address of the desired LCP to the Distr~bution Card in the selected Base ~odule~ At th2 same time~ the IOT sends i'Address Sel~ct" to all ~ase Modules in t~e system. The Distribution Card that recei~es both -the Address Select and Cha~lel Select begins a "Poll Test" and responds to the IOT withan "LCP Strobe"; the Distribution Cards that received the,Address Select only, consider it as a "busy" signal, and they ar~ inhibited from communication with the IOT~ ~hen the IOT 10t receive~ the LCP Strobe, it drops the Channel Select.
W~en the ~istributiGn Card recei~es an "Address Select"
and "Channel Select", a signal i9 generated which enables the LCP address to be placed into an LCP address regiqter in the Distribution Card. The BCD (Binary Coded Decimal) output of the LCP address register is decoded to enable one o~ eight line~s. Each line represents one LCP in the Base Module.
~hen an LCP detects that its address line is active, then that LCP responds to the Distribution Card wlth the signal LCPCON meaning ~LCP connected". ~hen this connected ~ignal is receiYed in the Distribution Card, a connect flip-j flop (CONF) is set. Then depending on the state of the I/O
send line (IOSND/ FIG 6C) from the connected LCP~ this will ~' cause an acti~ation of control lines for either receiYing data or sending data as between the LCP and the IOT
~ (FI~. 6C).
`~ If a Distribution Card detects the absence of Channel , Select, it responds to the IOT with the LCP's status, ~` j accompanied by a strobe. The LCP is now connected to the i ` ~ 6~ -: ' , ~ ~ . . .

IOT and remains connected ~m-til the IOT drops Address Select,;
the Distribution Card takes no ~urther part in the IOT-LCP
COm~lni Cationg .
r~e abG~.~e events show the s-teps leading to ~ successful "connection~ attsmp-t; however, the connection attemp-t could ha~e failed ~ue to one o~ the follo~ing causes:
(a) there was no LCP at the location addressed or the LCP at the address location was off-line;
(b) the LCP was bucty, that is the LCP status count was not O or 2 or 3;
(c) the port w~s ~usy, that 19, a second Distribution Card ill the 3ase Module was busy;
(d) a parity error was detected in the address.
The detection of any of these errors would cause the connectîon ttempt to be aborted and a ~esult Descriptor indicative of the type of failure to be written and sent to I the Main System in lOmr o~ Memory 10 ~FIG. 3).
- In subsequent discussions, reference may occasionally bte? made to specific flip-flops and signal le~els which are not ~pecifically shown within the block diagrams. Since the design and use of such elements are well known, it is considered to be redundant and overcomplex to show all such elements.
.~ ?t:
_.
An LCP, after ha~ing been co~1nected to the IOT 10t and receiving the Command Descriptor and the Descriptor Link, may "disconnectl' from the Main System 10 in order to communicatfa with its associated peripheral de~ic~, such ~9 5~. If t~at LCP subsequ0ntly requires access to Memory 10~, ;' ' , - 7 - ~

?
. i - , .

it sends ~ re~ue~t ~C~RQI oye~ to the Dist~i~ution CardqThe "Poll Request" is the ~e~hod b~ which t~e Dist~ibution Caxd~
in response to the LCPIs xeques~, attempts to ~econnect the LCP to the IOT.A num~er o~ e~ents occur during a "Poll Request" operation.
I~ se~eral LC~s ~ithin the B~se Module 20O simultaneously request access, the Distribution Card 20Od determines which one of them is to gain access by checking their prio~it~ levels;
thus, the requesting LCP ~hich has the highest priority level Cthis priorit~ selected at installation time~ is given access to the Distribution Caxd. This priority level is called '5Base Priority" as it involves which LCP has what level o~ prioxity as among the eight LCPsreSiding in that particulax Base Module Once the "Base Priorit~" is resolved,the Distribution Card assigns a "Global Priority''Cwhich has also been assigned and . . .
selected at installation time~ to the re~uesting ~CP A The "Global Priority" establishes the priority xank between dif~
erent Base M~dules in the overall system rather than just the priorit~ rank of LCPs in one single Base Module.
The Distribution Card 20Od contains a sexies o~ pins or socket-type connections which are connected to each indivi-dual LCP. These pin-socket connections can be ~umpered ~y a field engineerl to a priority encoder which assigns an internal base priority number from ~ero ~low~ to seven (highest~ to each LCP. Thus, if several LCP's in the same Base Module request Connection concurrently~ then the Distributi~n Card con~rol means will put thxou~h the LCP
with ~he highest priority.
Another set o~ pin-sockets on the Distribution Card ~ 30 are connected to e~ch LCP. These are "jumpered" or i nstrapped" by a ~ield engineer so that each LCP is ~iven a .
~ ~ 71 ~

"globall' or exte~nal priorit~ number to pe~it the Input/
Output Translatox intex~ace o~ the Main S~stem to select amongst LCP/s w~ich reside in di~erent Base Modules of the system~ Thus~ ~hen the.".gl~,bal" prio~ity number is ~eceiYed by the IOT r and there are concurxent xequests ~rom ot~er LCP's in other Base Modules, the IOT ~ill select the LCP with the highest global pxioxit~ numbex, but this .occurs only after internal,base priority has been resolved by the.Distribution Card.
Those Distribution Cards recei~ing requests from their associated LCPs~ each send an "Intexrupt Sign~l" ~P~ST4~
o~er to the IOT 10t. ~ee message level inter~ce ~IG.5E
and Table ~ hen the IOT 10t detects the signal IP~ST4 it begins the "reconneation" sequence ~nd sends a signal CAccess Gxantedl to all the Base Modules in the s~stem. The "Access Granted" signal causes those Distribution Cards that sent the IP+ST4 to the IOT.10t to begin their indiYidual 'rPoll Request" algorithms~
In response to the "Access Granted" signal, the requesting Distribution Caxds~ send theix indi~idual Glohal Priorities over to the IOT 10t~ The IOT compare~ the.Global .' , .

~;
.

. . i ~ 71a ~ , ~6~

Priorities of t~e requesting Distribution Cards ~tha~
sends the Cha~nel Select signa] over to the requesting Distributiorl Card ~hich has the hi~hest Global Priority one clock-time later) and the IOT sen~s an ~ddress Select signal to all Distribution Cards in the system. The Distribution Card that recei~es both the "Channel Selectl' and the "Address Selec~" responds to the IOT with the LCP Strobe~ then sets its LCP Address flip-flop, thus driving the specific address line-of the requesting LCP. ~hen the LCP detects that its own address line is acti~e, it then responds to the Distribution Card with the LCP connected signal (LCP~ON).
! ~pon receipt of the LCP Strobe, the IOT 10t drops "~ccess Granted~ signal and the "Channel Select" signal; and when the Distribution Card detects the absence of the "Access Granted~ and the "Channel Selectn and detects the presence of IGPCON, it then assumes a connection to be completed and responds to t~e IOT withan LCP Strobe, accompanied by the I~P Status Count and the Descriptor ~in~.
~he Poll Re~uest i9 now complete; the Distribution Card takes no ~urther part in the LCP-IOT co~municatlon. The ECP
~nd the IOT continue with the r~connection sequence until ~he LCP is connected, after which control is passed to the IOT
Data Transfer Module lOtc~ FIG~5Co The LCP remains connected until the time when the IOT drops its "Address Select" signal.
! 25 Error Checks:
Each tr~nsmission between the IOT and a particular LC~
is checked for errors. The e~ror checking methods use~ are (a) vertical parity checking on each word trarlsmitted, and (b) longitudinal parity chec~ing on each block trans~itted.
' ' .

~ 72 -, $ -(^\l `) 3~6~

~ ~ al Parity:
.
In "R0ad" operations, the I,CP sends info~nation to the IOT 10t on 16 me sage le~el interface (~IL~) data lines, (~IG. 5E) aGcompanied by~the parity bit on the ~LI parity line,FIG. 5E. The data and parity lines go to a parity generator~checker Dn an IOT base driver card. In ~Read"
operations, the parity generator checker is used to count the number of 1 bits on the MLI data and parity lines, I~
- the total number of l-bits (including the parity bit) is odd, then parity is correct and a signal term (P~ROK, ~IG.
6D) from ~xit~ nex~tox 48 is genex~ted. 1~ the total nu~be~
of one bits is even, then the PAROK si~nal is not generated; the - absence of PAROK at the time that data is received,causes the IOT
to~set a vertical parity error flip-flop (VPERRF).
Similarly, in ~Write" operations the 16 data line5 ~rom ~he Main System 10 are bussed to a parity generator-checker on the IO~ base driver card. The data on the 16 lines is e~amined and if an even number of l-bits is detected, the term PARGEN is generated. This PARGEN signal is`then used to forc~e a "1" bit onto the message level interface p~rit~
~ line to accompany the data to -the LCP. On the LCP ~ase '. Distribution Card~ -the state of the parity bit ~ontrols the ~' parity generator_checker circuit. The paritr generatar-~ checker circuit examines the states o~ the 16 ~ata lines and :` 25 generates PAROK if the total num~er of l-bitsS .including ` parity, is ocld.
( ~ tudinal ~ar.it Check~
Longitudinal parity checking is an error detectian method ;.r ~ch a check word generated by a sending unit is -- ~

co~pared to a check word ~enerated in the sa~e manner by a receivj.ng unit. These check words are O~nerated by -creatin~
sach word in the transmisslon as a 16-bit number, then perfor~ing an exclusi~e 0~ operation (bi.nary addition without carry) of each wor~ in the tr~nsmission. At the end of the . transmission, the sending or transmitting device sends the ,~ check word it has assembled over to the recei~ing device.
! If there have 'oeen no errors in the transmission, the addltion : of the check word from the transmitting devlce to the check word in the receiving device resuits in a sum of no". Thus, i~ the sum is not ~10", a longitudinal parity error flip-flop i8 flagged ~PE~
s A~ was discussed in con~ection with EIG. 6B, the LCP
was provided with LPW circuitry 24 . Likewise 9 there is longitudinal parity checking circuitry in the IOT lOt. Thi9 circuitry connects in a parallel path to the data bus shown as the lower 16 lines o~ FIG~ 5E.

\
''j ' \ /
'. ' \ /

~ / \

\~

.

: ~ .

The Line Control Processor ~LCP) J such as element 200 , may be better understood with reference to ~IG. 6C which - represents a basic block diagram of the major elements in~olved in additioIl to some specific details with re~ard to the ~ buffer such as 25 0 of the LCP, 2000~
The LCP buffer 2500 is a random access m~mory (RAM) which is f~ctionally 256 bits (0-255) wide and 18-bits deep.
It can thus hold 256 words cf 18~bits each. In one typical embodiment, the buffer 25 may have a section designated buffer A, 25a, ha~ing provisio~ for 90 longitudinal ~ords of 18 bits each; another section designated 25 i; a Com~and Descriptor C/D section designated 25c; a buffer area B, 25b which may typically be 90 words long, (i.e., from address 128 over to address 218); another buffer area designated 25 2; a R~sult Descriptor R/D area 25r; c~lother area designated 25x3; and a Descriptor Lil~k D/L area designated 25d.
~he ~l buffer 2~oo is addressed by a memory address register 36 having a system address register section 36S and a device address register section 36d~ which colm~unicate to the buffer 25 via an eight-bit address bus, B8. The R~l bu~fer 2500 is functionally composed in the vertical direction (FIG. 6C) of 16-bits plus a parity bit, plus an eighteenth bit called an "end flag bit~, th~e end flag bits residing in a storage section designated as 25 .
. A "data bus't 47 provides a data input and output channel for the buffer 25 to comm~lioate to the Main System 10 through the system interface lG~ic 21Si; and fo~ the ~uffer 2500 to communicate to its peripheral unit via a device interface 22di. The system interface logic 21Sig the device ~, ~ .

interface logic 22di~ and the common logic 22C schematical'y represents blocks which refer ~o more specific elements ~Ihich are described in connection with FIG. 6D.
Referring to ~IG. 6~, there is sho~m a "message block"
~; 5 of the type used in the LCP buffer 25 of ~IG. 6C.
As mentioned with ths disc.-llssion of FIG. 6C in regard to the R~ buffer 2500 ~ this is typically a message bloc~ of ~n" words~ w~lich block provides ~0 words (or n = 90) for data storage; and also there may bs provided three words for ~` Reqult Descriptors R/D; there may be provided three word ~ locations for Command Descriptors C/D; and there may be one word location for CorMnand ~eCsages C/M.
FIG. 6~ also shows the basic word format, in that a word is composed of four digits which are: A, ~, C, and D
plus a parity bit ma~-ked VPB (vertical parity bit), which ! normally make-q a total of 17-bits per word.
A~ seen in the drawing of FIG. 6F, the four digits ' A, B, C and D are each made up of ~our bits designated as ¦ ' the "8" bit, the "4" bit, the "2" bit, and the "1" bit.
In FIG. 6C, the buffer 2500 iS a~ 90 provided with an 18th bit or ~end flag" bit which is placed in the location de~ignated 25 of FI&. 6C.
The central or Main System 10 communicates with the peripheral terminal unit via the L5P. ~he LCP provides the meanq for transferring control i~fo~mation and data from the ~ain System 10 to the peripheral terminal units, such as 50, ~ and vice-versa. The LCP looks at the Command Descriptor ``' C/D received from the Main System io and sets itself up to perform the operation required if it is sensiti~e to that . ~ .

particular command. It ~150 transfers the same Command Descriptor C/D unmodified to the pe,ipheral terminal unit.
The peripheral terminal llnit acts upon the Command Descriptor C/D and returns Result Descriptors R/D to the ~ain System 10 via the LCP. T~e message block and the word formats have been shown in FI&. 6F, Typical Command Descriptors C/D and Result Descriptors R/D will be shown subsequently hereinafter.
The LCP accepts the Command Descriptor C/D transmitted by t~e Main System 10. The C/D con-tains a digit o~ the OP
code, 3 digits of variants, and 6 digits o~ C address. The Command Descriptor C/D is received by the LCP via 4 digits per transmission for a total of 3 words (4 digits per word).
The two least significant digits contain all zeros. With each word there is a vertical parity bit ~VPB) and the entire C/D is followed by a longitudinal parity word (LPW). Should I a parity error be detected on transmission of the C/D, the ! LCP ~ill branch to a Result ~escriptor R/D mode and report a ¦ descriptor error to the Main System 10.
¦ The random access memory buffer 25 (R~M of the LCP) buffers the entire Command Descriptor, the vertical parity ¦ bit and the longitudinal parity word within the LCP~ Line Control Processor.
The LCP examines the first wcrd of the Command Descriptor C/D and determines whether it is an ECHO OP, HOST LOAD OP~ or I 25 READ NO timeout OP. If it is one of these, it sets the 'i~ appropriate ~lag.
Descriptor Link (D/L~:
~ollowing the receipt o~ the Command Descriptor C/D, the Line Control Processor LCP proceeds to accept the Descriptor : .

.
~ 77 ~

; ( 3 ~ 3 Link D/L. This is a two word tr~sm:;ssion followed by a longitudinal parity word LPW. Should there be an error, t~e LCP branches to the Result Descriptor R/D mode, and reports a descriptor error to the System 10 The random access memory ~I of the buffer (such as ~500) acts as the buffer for the entire Descriptor Link D/L, the vertical parity bit (VPB) and the longitudinal parity word LPW.
Disconnect Mode:
~ .
Following the receipt of the Descriptor Link D/L, the LCP goes to the "disconnect moden.
Reconnect ~Iode If it is an ECH0 OP, the Line Control Processor LCP
proceeds to "reconnect mode" and starts operating on the .15 ECX0 OP which involYes the receiving ~f two buf~ers of data ,, .
~ea~h 180 bytes, or 90 words of 16-bits) and the tr~nsmitting of the same data back to the System Memory 10 .
If it is other than an ECH0 OP, the LCP examines the readiness of the peripheral terminal unit. Should the peripheral de~ice be in the "not ready" state, the LCP
:` . .-branches to the Result Descriptor R/D mode and reports this to the System 10.
If the peripheral device is "ready" the LCP starts communicating t~e Command Descriptor C/D to the peripheral device, while at the same time branches to the "idle" state to make itself available for a possible nConditional Cancel OP". The Line Control Processor LCP stops in this nidle"
state until one o~ two things happen:

~ . , ; - 7~ -~ ~ !

1. The perlpheral device sets up the Line Control Processor LCP to a "data transfer" s-tate.
2. The System 10 communicates a "eonditional Cancel OP" or an Unconditional Cancel.
If it is number 2 above, the Line Control Processor LCP accepts one word from the System 10 followed by the longitudinal parity word LPW, and the LCP determines if it is a Yalid Conditional Cancel OP. In any case the LCP
communicates this to the peripheral device. I~ the situat;on in~ol~es number 1 above, the LCP branches back to the - ndisconnect" state~ where data trans~er between the LCP and its peripheral can occur.
~fter transmission o~ the Command Descriptor C/D to the peripheral, the LCP is dri~en by the peripheral device "state", which de~ines the operation mode and the memory requirements.
Data is transferred in "message blocks" together with a longitudinal parity word (LPW) of 16-bits following each blocX and with a parity bit on eYery word (except in a disk pack controller si~uation, the message block would consist o~ a segment). If the Line Control Processor LCP detects an error on data received from the peripheral de~ice or from ~he Main System 10, it reports this information to the ~eripheral de~ice and then branches to ~he Result Descriptor R/D mode and reports it to the Main System 10.
25 . I~ the "Read~ mode, the data transfer between the Line Control Processor LCP and the peripheral device is dependent on the requirements of the peripheral device-On the other hand, data transfer between the LCP and Main Memory 10m is dependent upon the memory access rate of the ~ain System 10~ Since the peFipheral ' q~ 79 -~ (-`i : ;`) device may operate in a "stre~l" mode, and the LCP ~ust compete with vther LCP's for access to memory, the LCP
alternates be-tween it's two buffer areas to acco~nodate the transfer rate of the peripheral de~ice, . Table VIII below indicates certain types of Command - Descriptors C/D which are used and acted on by the LCP.
All other C/D's are transpare~t to the LCP and pass throu~h to the peripheral device:
. ~ T~BLE VIII
Co~mand Descriptors The LCP is transparent to all Command Descriptors except for the following as determined ~y testing the first word of the C/D: -1. E~HO OP ~bit Al is true) 2. HOST LOAD (A4 and B8 are true) 30 READ NO T/O (timeout) (A8 and B8 are true)

4. CONDITIONAL C.~NCEL OP (A2 and B8 are true).
~. UN~ONDITIONAL C~NCEL
OP code digits of the C/D are defined as follows:
Read (A8) - Any operation where data is transmitted from the LCP buffer to the ~lain System.
., `. ;. (1000) Write (A4) - Any operation where data is transferred ~ from Main System Memory to LCP buf~er.
; 25 (0100) I Test (A2) - Any operation where no data transfer; takes place between LCP and System . O Memory but results in a R/D storage ¦ ` in System Memory. (0010) Echo (Al) - Operation that results in receiving a ~ message block from System Memory and then ; transmitting the same block back to System `i Memory. (0001).
~ .
3 . -.

;' ~ 80 _ 6~2 ~

Normally Result Descriptors R/D are generated by the peripheral unit aIld accepted by the LCP in one, two or three words. When the LCP generates a R/D,only one word is sent to the Main System 10. Table IX shows the conditions for the LCP to generate a Result Descriptor:
~ABLE :~g Result Descriptors Bits A8 Not Ready ~4 Descriptor Error A2 System Yertical Parity Error Al . S~stem LPW Error .
B8 Time-Out B4 Remote DeYice ~er-tical Parity Error B~ Remote Device LPW Error Bl (blank) - , '\
- , . .
~, ,~

Referring to FIG. 6C with respect to the lines between the device interface 22di and the peripheral unit, the peripheral device unit may be pro~ided with a port interface which may be designated as a DDP or device dependent port interface, 5d~ which is tailored to the requirements o~
each specîfic type of peripheral device.
The LCP communicates to the peripheral via the DDP in an asynchronous mode. The "Write" operation is defined as a tran-sfer ~here the LCP is writing into the peripheral device unit. The "Read" operation is defined as a transfer where the LCP is reading from the peripheral device unit.
Referring to FIG. 6C the line marked HTCL/ may be designated as the Host Transfer Control Le~el, and when the LCP ~Writes" into the peripheral de~ice unit, this signal is the asynchronous level, which signifies the presence of data on the data lines. This level is de-activated by the peripheral unit sending DML/ (peripheral ~essage level) or I by sending DINTL/ (peripheral device interrupt level) to the LCP.
~hen the LCP is "Reading" data on a Result Descriptor R/D from the peripheral unit, this ETCL/ signal i9 the ~ asynchronous acknowledgement that the data on the data lines ¦ has been received by the Line Control Processor LCP. Upon receipt of this le~el, the peripheral device unit must de-r 25 acti~ate D~L/ or DINTL/. When the peripheral unit causes the de-acti~ation of DML/ or DINTL/, then the LCP de-acti~ates HTCL/ (the Host Transfer Control Level~.

~hen the peripheral device unit drives the LCP to the Co~mand Message C/M mode, the Host Transfer Control Level H~CLJ is sent to the peripheral device unit when the LCP's buffers are empty and no system terminate has been detected.
The XTCL/ n~st be answered by the peripheral de~ice ~nit ~ith a DINTL/ and a change of-state.
The line in ~IG. 6C marked XINTL/ is designated as the Host Interrupt LeYe] and is used by tha LCP to indicate to the peripheral unit that the LCP wi~hes to interrupt the operation. The response to this level by the peripheral de~ice must be DINTL/ and a change-of state, to which the ` LCP responds by de~activating its Host Transfer Control Leve~, HINTL~. Following the detection of the trailing edge of ~INTL/, the LCP will respond to the new mode of operatian desoribed by the state line shown on FIG.6C as ST-4/, ST-Z/~
ST-l/.
~` When an interrupt from the System 10 is activate~ ~ ~he ~Write" mode, the Host Interrupt Level HINTL/ signifies that the last word of data has been transmitted and the LPW ~s Q~
the datà line of bus 47. The peripheral unit needs to respond to the interrupt with a DINTL! and a change-of-state~
In the "Read" mode when the LCP detects the "Read Terminate~command",the LCP will activate the ~ost Interrupt Level EINTL/. In the Command Message C/M mode, the LCP wil~
activate the Host Interrupt Le~el HINTL/ if a "Read Terminate"
has been detected.
The line of FIG. 6C designated HCL/ refers to "Host .. ~ .
Clear~ which indicates to the peripheral unit that the LCP
' - " , . .

' - , ;.

~ 3 -is being cleared by the Main System 10, or that a parity error has occurred during a read.
A combina'ion of the Host Transfer Control Level and the Host Interrupt Level (~TCL/ - HINTL/) indicates to the peripheral unit the presence of a Host Load Command Descriptor C/D. The peripheral unit responds by activating the line marked DINTL/ ~peripheral interrupt level) and the Status Count ST = 2; the LCP acknowledges by d~-activating both levels of HTCL/ ~ HINTL/~ Following the trailing edge - 10 of DINTL/, the LCP transfers data in the "Write mode".
In FIG. 6C a bidirectional data bus Bd is provided having 16 data lines and a parity line bet~een the LCP and the peripheral unit. When controlled by the LCP, these lines are active as long as the Host Transfer Control Level HTCL/ is - 15 active. ~hen control is held by the peripheral unit, these lines are active as long as the peripheral device message levei DML/ is active. The direction of transfer is determined by the status of the peripheral unit. m e line designated D~L/ refers to the peripheral device message level and i3 a unidirectional line~ When the LCP is reading data or a Result Descriptor R/D ~rom the peripheral unit to the LCP, the peripheral device message level DML/ is used a9 a tra~sit signal to indicate the presence of stable data on the data - lines. When the peripheral device receives a Command -~25 Descriptor C/D or data from the LCP, this signal, DML/~ is used as an acknowledge level for data.
The peripheral device (via its port interface~ uses the DINTL/ (peripheral interrupt level) to request the LCP
to change its mode of operation. This is done by activating .

DINTL~ and presenting the proper state on the state lines, ST-4/, ST 2/, ST-l/. The state linos must be stable during the time that DINTL/ is active.
n the "Write Mode":
DINTL/ is the acknowledge level to the Host Transfer Control Level HTCL/ and the LPW data word; or else it is the response to XTCL~ or HINTL/ in the Command Message C/M mode.
DINTL/ will cause a change-of-state to occur for either the above. When the LCP is writing into the peripheral unit, the peripheral device interrupt level DINTL/ is based on the leading edge of HTCL/ or HINTL/. DINTL/ is de-activated by the trailing edge of these signals (~TCL/ - HINTL/).
In the "Read Mode":
The peripheral interrupt level DINTL/ is a no-data transfer "strobe~ used exclusively to change states, DINTL/
j i acknowledged by the Host Transfer Control Level HTCL/ in i the Xead Mode. When the LCP is reading from the peripheral device unit, the peripheral device activates DINTL/ instead ¦ of the peripheral message level D~/, and de-activates DINTL/
when the peripheral unit detects the leading edge of the Host Transfer Control Level HTCL~.
In the ~ost_Load Mode~
This mode involves the transfer or loading of data from the peripheral device, as 50 9 FIG. 6C, into the LCP (Host) ~ 25 for the "Read Mode" and vice versa for the "Write Mode".
¦ The peripheral de~ice interrupt level DINTL/ is the ; acknowledge level to HTCL/ - HINTL/ as the Hos-t Load Command.
The peripheral device activates DINTL/ and changes to State 2 (Table X)~ The LCP acknowledges this by de-activating ~; .
` .

~, ~ ~ `

both HTCL/ - HINTI,/, and if in the "Write Mode", starts writing into the peripheral device memorr. To interrupt this mode the peripheral de~ice unit 5G activates DINTL/
in the ~ame manner as in a regular "Write Mode".
The "State" lines:
In ~IG. 6C, these unidirectional lines ST-4/) ST-2/, ST-l/, indicate to the LCP the state of the peripheral device, and from this, the LCP determines what kind of operation mode is required. For example, in a typical embodiment, there may be eight states, 0-7, as seen in Table X, for the peripheral de~ice which might be used to indicate the following conditions: peripheral device not on-line; Read operations; Write operations; Result De.~criptor; Command Message (C/M); reset LCP timer (RT);
ready or writing Command Descriptor (C/D); last word of a block or the Result Descriptor and longitudinal parity word (R/D-LPW) is next to be transmitted.
. A ty~ical coding system for the state lines from a typical peripheral de~ice unit is shown herein below in ` 20 Table X:

`! / ~ -``I / .

.

- - 86 - .

~D37~V~ .,, 0 .
p _ = p :`, .' R h O ~ o o ; ~ .

p ~D h . ~ ~ ~:1 m 1~ ` , I O ,1 0 ~1 0 ~O ~1 ' i, , U

I O O -I -I O O
I
I .
I O O O O
~ u) I ..

1 ~ lo ~ w~
.
, - ~ , X6~

The interface discipline betwesn the LCP and the peripheral device unit via the peripheral device unit port interface(DDP 5d~ FIG. 6C) may again be looked at in terms ~- of a "Reading Mode" and a "Writing Mode".
Reading Mode:
With the Line Control Processor LCP reading from the peripheral device unit (State = 1 ~ 7), the peripheral device unit (as 50, FIG. 6C) places a word on the data lines - and activa+es the perip~eral device message le~el DML/. The LCP ac~nowledges this by acti~ating the Host Transfer Control Level (HTCL/). The peripheral device unit now de activates DML/, and then the LCP de-acti~ates the HTCL~. This process continues in State = 1 until:
1. The LCP activates the Host Interrupt Level (HINTL/).
The peripheral unit acknowledges by de-activating the ~ peripheral message level (DML/), if active, and activates ¦ the peripheral device interrupt level (DINTL/) ~ith a change-of-state. This indicates to the peripheral de~ice that the 1 LCP has a ~Command Message" C/M to send to the peripheral ¦ 20 device.
~ 2. The peripheral device activates the peripheral de~ice `~ interrupt le~el DINTL/ instead of the peripheral message le~el DML/, with the proper change in the State Lines. The LCP
acknowledges by activating the Host Transfer ControI Le~el 3 25 (HTCL/), and, following the de-activation of DINTL/, it de-acti~ates the Host Transfer Cont~ol Level HTCL/ and goes on to the proper State. DINTL/ does not trans~er data on the data lines.

.

, i ,~ , z~

3. When the peripheral device detects it i3 transmitting the Last Word of a block, the perip~eral device changes to Status ST = 7 with the leading edge of DML/. The LCP
answers the peripheral device with a Host Transfer Control ; 5 Level (HTCL/) and expects the next transfer to be the longitudinal paPity word LPW. The LPW is transmitted with the peripheral message level DML/ and answered ~ith a Host Trans~er Control Level (HTCL/).
4. If the LCP detects a vertical or longitudinal parity error, the LCP will not acknowledge the peripheral message level DML/ from the peripheral device. Instead the LCP will generate a ~ost Clear Level (HCL/).
In the Writing Mode:
If the LCP i9 writing data into the peripheral device (State = 2 + 7~ the following actions take place:
` The LCP places a word on the data lines and activates l the IIost Transfer Control Level (ETCL/). The peripheraldevice acknowledges by activating the peripheral device ~; - message level (~ML/). The LCP now de-activates the Host~ 20 Transfer Control Level (HTCL/), and then the peripheral ¦ de~ice de-acti~ates the peripheral message level (DML/).S Thig process continues (Table X) in Status ST = 2 until:
'~ 1. The peripheral device changes state to ST - 7~ then activates the ~eripheral message level DML/ which flags the ~ 25 LCP that the Last Word of that block has been received. The i next word in the data lines must be a longitudinal parity word LPW when the Host Transfer Control Level HTCL/ becomes active again. ~hen the peripheral device activates the peripheral interrupt level DINTL/ instead of the peripheral device message level DMI,/~ accompanied by a change in the ~ State Lines.

. .

~316~

2. At ST = 2 or ST - 7, the L~P activates the Host Interrupt Level HINTL/ instead of the Host Transfer Control Level HTCL/. In this mode, HINTL/ signifies an interrupt and that a longitudinal parity word LP~ is on the data line~.
The peripheral device acknowledges by activating the peripheral interrupt level DINTL/ and a change of-state.
The LCP de-activates the Host Interrupt Level HINTL/ and goes to the propes mode after DINTL/ is de-activated.
In another mode called the "Result De~.criptor R/D Mode", the LCP reads a Result Descriptor R!D from the peripheral device (State = 3 + 7). When in the R/D Mode, the LCP is reading the Result Descriptor on the data lines from the peripheral device. The Result Descriptor R/D can be from 1 to 3 words long plu9 a longitudinal parity word LPW. '~he first and second words of the 3-word Result Descriptor R/D
are read in Status ST = 3. The last word of the Result Desc~iptor R/D is read in 5tatus ST = 7. The peripheral device message level D~./ signi~ies there is stable data on the data lines. Each Result Descriptor R/D word transferred i9 then ac~nowledged with a Host Tran fer Control Le~el HTCL/.
If a l-word Result Descriptor R/D is received by the LCP, then data transfer occurs after going from Status ST = 3 to Status ST = 7 together with a pcripheral device message level DML/ which signi~ies a l-word Result Descriptor R/D. The next word on the data lines i8 the R/D longitudinal parity ~ord LPW which is strobed b~ the peripheral device message ~ level DML/. After the LCP finishes reading a complete Result Descriptor R/D together with its appropriate longitudinal .

; 9 ~

.", ~ . .. ,"_, . ~, . . .

~'F ~ r~

parity word LPW~ the peripheral device returns to Status ST = 6. It can now accept a Co~mand Descriptor C/Do Command Messa~e C/M Mocle:
This involves -the situation in which the LCP is writing a Command Message into the peripheral device (State ST = 4), When the LCP is in the "Read" mode and is directed to the Command Message C/M mode (DINTL/ + ST = 4)~ the LCP continues to send data to the Main System 10 until:
1. The"read-system terminate" is detected which results in activating the Host Interrupt Level HINTL/ or:
2. Data buffer areas A and B (of buffer 2$oo~ FIG- 6C) are empty and the "read-system terminate" is not detected.
Thl~ causes the LCP to activate the Host Transfer Control Level HTCL/, indicating that the Main System 10 expects more data.
The Reset Timer ~R~T) Mode:
, Thi~ occurs when the peripheral device resets the LCP
I t~mer (State ST = 5). A change-of-state to ST = 5 resets the I LCP timer. This change-of-state occurs without a strobe.
The peripheral device unit must remain in ST = 5 for at least 500 nanoseconds.

In this case the LCP is writing a Command Descriptor C/D into the peripheral device (State - 6~. In this send Command Descriptor Mode C/D, the LCP writes 3-words followed ~ by a longitudinal parity word LPW. The Host Transfer Control J Level HTCL/ that accompanies the C/D and LPW i5 acknowledged by the peripheral device interrupt level DINTL/ and a change to the proper state.

.

;
9 ~. _ This is the State - 7 (of Table X~ and during a "Read' operation with ST = 7, the LCP is reading the ]ast word of a block ~f data ~or else a ~ssult Descriptor R/D~ from the peripheral device. ~he next word will be an LPW. During a "Write" operation with ST = ~ the LCP is writing the last word of a block into the peripheral device. The next word will be a longitudinal parity word LPW.
Condit~
After the LCP writes the Command Descriptor C/D into the peripheral device unit and before the peripheral device . changes from Status ST = 6 with the peripheral interrupt level DINTL/, the Main System 10 can terminate the operation ~OP) by issuing a "Conditional Cancel". In this case, the ; 15 LCP de-activates the Host Transfer Control ~evel HTCL/ and then activates the Host Interrupt Level HINTL/ as long as the Status ST = 6 and ~INTL/ is not active.
` Unconditional 5anc 1-.
The Main System 10 can generate an "Unconditional Canceln. This causes the LCP to generate the Host Clear Level HCL/ to the peripheral device. No acknowledgement is required from the peripheral device.
'i \ /
`:`' ~ ~

.

' _ 92 -.. ~' `? ' ~

, The LCP (Lin~ Control Processor) Subsystem consists of a number of individual LCPs which communlcate to the ~ain System 10 through the IOT lOt. ~ile each of the several LCPs ha~e basically the same design alld provide the same basic system functions~ there are variations o~ a minor ~ature as between the various types of LCPs, since each LCP
is tailored to me~t the operational requirements of the particular peripheral terminal unit that it s~rvicesO
~~he discussion following herein will involv~ an operational description f on~ preferred embodiment of a particular LCP ~hioh ls provided fo~ a peripheral terminal unit kno~n as the "Supervisory Terminal".
~he necessary ~unctional elements of the LCP include registers, coun-ters, encoders, decoders, busses, logic 15 -elements, etc. In addition there is a large scale integrated (ISI) receiver~transmitter for implementing communication between the ~CP and its peripheral terminal unit~ Within the LCP, there are functionally two divisions that are used ~or communication between the LCP and the Main System 10.
They are designated as the nread module~ and ~write module".
~hese modules exist "functionally", but they are not ~eparato components, since many of the logic le~els of which ~hey are composed are shared by both modules. The "read module" is used to transfer data from the LCP over to the ~aln System 10, and is active when the transmit flip-flop (XMITF3 in the ~CP is set. The "write module" is used to transfer ~ata from the Main System 10 over to the LCP~ and i9 acti~e ~hen the recei~e flip-flop (REC~F) is set.
i Functionally, the components of the LCP are contained in three major sections: (A) Terminal Control; (B) Data Flow;

.

.

and (C) System Logic Section. In order to unders.tand the means by which -the LCP communicates with the Main System lO
and with the ascociated peripheral terminal uni-t, such as 50, the functional characteristics of the following co~ponents will be discussed:
A. Peripheral Terminal Control Section ~ 1. Universal Asynchronous receiver/transmitter : (UART).
- 2. UART MultiplexorO
3. Block check character register (BCCR).
4. Block check character decoder.

5. End eode decoder.

6. Memory address register.
B. Data Flow Section ;~1$ 1. Input ~ultiplexor `2. OP code register.
l30 Variant register.
4. Valid OP encoder.
5. LCP buffer (RAM).
6. Terminal bus ~ultiplexor.
~ 7. Terminal bus.
¦ 8. Vertical parity generator/checker.
9. Data Latch register.
lO. Longitudinal parity word (LPW) register.
ll. LPW encoder.
12. End code decoderr .
. .
' - 94 ~

. C. System Lo~ic Section 1. Status Count {STC~ xe~ister.
. . 2 STC decodqx.
!'` The ~bo~e mentioned functional components ~ill be understood ~ith ~e~exence to FIG.6B, 6C~ ~D, 6E and ~F, with particular references to FIG..6D.
Examples o~ types o~ interconnections between periph-eral devices ~nd I~O interfaca units may be found in U.S.
Pa~ents, such as 3,510,843;3,S14,785;3,~26,878. Examples of the circuitry in~olved in communication between remote units and corresponding buffer registers in a typical fash-ion can be found ~y reference to U.S. Patent No. 3,390,379.
~ ith reference to FIG. 6D and the Peripheral Terminal Control CSection A~ previously mentioned, the universal asynchronous receiver transmitter ~UART~ 31 is used as the interface ~etween the asynchronous serial data channel of the terminal unit device interface 2~di and the parallsl data transmission channel o~.the LCP. The transmitter section of the UART 31.converts a parallel data charac~er and the control levels into sèrial in~ormation containing a start bit, data, a parity bi~, and a stop bit. The xec~iver section of the UA~T 31 converts serial in~ormation, containing a start bit, data, a parity bit, and a stop bit, into a parallel data character~ ~he UART 31 generates a parity bit for information transferred to the termlnal unit de~ice interface 22di, and it~also checks tha ~ertical parity of information received from the device inter~ace . terminal unit 22di.
The UART 31 has provisions:~or selecting various character lengths, odd ox e~en parity ~eneration~checking, and a choice o~ one or t~o stop bits- Fox use with a parti~
cular LCP, the UAR~ 31 has options selected to pro~ide the -. ~ following characteristics:
a char~cte~ containin~ seven data bits;

; (b) generation/checking of even ~ertical parity;
(c) one stop bit, . The UART Multiplexor 27X accepts an 8-bit character fro~ either the AB (first two) digits of the terminal bus 47 or from the block check character register (~CCR) 33.
Ihe selected input is sent to the parallel data input bus of the UART 31. The UART Multiplexor 27X is used only for the transfer o~ data or for a block check character from the LCP over to the terminal device interface 22di.
The Block Check Character Register (BCCR) 33 is a - register which consists of ei~ht separate flip-flops operated - in the "toggle" mode, with inputs conneeted to the AB digits of the terminal bus 47. While the LCP i9 transferring data to the terminal de~ice interface 22di 9 the BCCR 33 accumulates a block check character (BCC) to be sent to the device ; interface terminal unit 22di. When the LCP is receiving data from the device interface ter~inal unit 22di~ the BCCR
33 also accumulates a "block check character" to be ehecked against yet another "block check character" (BCC) sent from 1 20 the device interface terminal unit 22di. The block check eharacter accumulation i9 started upon the receipt of the j first eharacter following a STX (start of text) or a SOH
(~tart of heading) character, and continues until an ETX
i (end o~ text) character is recei~ed. Only messages and ~. 25 control sequences containing a STX or a SOH character will ¦ eause a block check character (BCC) to be accumulàted.
Ihe aeeum~lation of the BCC consists of applying each eharacter being transferred to the input o~ the BCCR 33 --and performing a binary addition without carry (Exclusive ~' ' ~ .
', , ' '~

: -` '`' 3 OR ~unction). Prior to each operation in which a ~C will be accumulated in the BCCR 33, the register is cleared. At the end o~ a data transfer, the exclusive OR ~ction is - ~gain performed bet~een BC~'s of the sending and receiving units. If no errors have occurred, both BCC' 9 will be identical and the resultant ~alue in the ~CCR 33 will be "all zeros".
The block check character decoder 34 receives the output .sr~
of the BCCR 33. At the end of a transmission from the peripheral terminal unit 50, a ~CC is received and checked against the contents of the BCCR 33. If the two BCC's are identical, then the output of the BCCR is equal to "all zeros" and the decoder 34 generates the BCCOE level (Block check character 0~) which is used in the BCC error logic.
~he me~ory address register 36 is an eight bit register which develops addresses for a 256 word L~P buffer 2500.
The register 36 is controlled so as to provide selective or ~equential addressing of the buffer, as required b~ the data transfer operation which is to be performed.
The Termination Card 20~t (o~ FIG. 2) provides a one~
` sccond timer which is enabled for operation only during a ; "read" operation when the LC~ is conditioned to receive data ~rom the peripheral unit, such as 50~ When enabling inputs are active, the timer alIows the peripheral terminal unit a one-second period in which to begin a transmission or continue an interrupted transmission over to the LCP~ If the one-second period elapses without a transmission from the peripheral terminal unit, a time-out flip-flop (T~OUT~) is set, generating time-out level (TIMOUTL), and the LCP then 6~
i .." ~ ,,. . I
initiates an end to the read operation by setting an end flip-flop (ENDF), HoweYer9 this til~er can be programmatically inhibited from operating by placing the proper code in the - variant-l digit of the Comm~nd Descriptor (FIG. 4B).
With reference to ~IGS. 6B and 6~ and the prior discussion regarding the Data Flow section of the LCP, (Section B), the input multiplexor 24Xl provides the ~election of a 17-bit word from three sources: the data input lines Bi, the output lines B25-from RAM data buffer ~50O
or the peripheral de~ice interface le~els 24m which are generated on the Maintenance Card (such as 200m~ ~IG~ 2) from the outputs of push-button switches on the maintenance panel. The selected levels received by input multiple~or 24Xl are transferred to the OP code Register 42-~and vàriant register 43, the ter~inal bus multiplexor 24 2 or the valid OP encoder 4~, as required by the operation to be performed.
~he OP code Register 42 receives the digital OP cade of : ~he Command Descriptor C/D, and in conjunction with the output of the variant register 43, specifies the operatio~-to be performed by the LCP. The Yariant register 43 recei~es the ~ariant digits contained in the Command Descriptor C/D and, - in conjunction with the output of the OP code register 42, specifies further details of the operation to be per~armed by the LCP.
The Valid OP Encoder 44 is a network w~ich receives Command Descriptor C/D information at its input; then, if the OP code digits and the ~aria~t digits 1, 2, and ~ coincide with va~ues representing valid operations for the LCP, this ercoder deveLops the valid OP (VOP) level, which enables ( ``?
.

the Command De~criptor C/D to b~ loaded into the OP cod0 register 42 and the variant register 43.
The L~P RAM buffer ~500 is made of a network of 18 R~l - devices~ each one of which has a capacity of 256 information bits. Reference to FIG. 6C will show more detail of the ~l buffer 2500. The buffer network can store 18-bits in each of its 256 address locations; 16 are clata bits, one ~lt is a parity bit, and one bit is an end-flag bit(25 of FIG. 6C) to identify a word location containing an ending code~
Referring again to FIG. 6D, the terminal bus multiplexor networ~ 24X2 provides selection of ~ 17 bit word fram four ~ources: the input multiplexor 24 1; the UART 31 parallel data output line; the LPW 24 register output, an~ the Re3ult Descriptor levels 24 d. The output of the terminal 1~ bus multiplexor networ~ 24 2 goes to the terminal bus 47.
Appropriate ~oltage levels are proYided to those TCP components, (~ch as the data latch register 49, vertical parity generator/checker 48, buffer 2500 9 ~PW register 24W~ decoder 52 and end code decoder 35 etc.~ which have input~ received from the terminal bus 47.
The terminal bus 4~ connects the output o~ t~e terminal bus multiplexor networ~ 24X2 oYer to the following components:
the data latch register 49, the LCP RAM buffer 250a, register 24w, the vertical parity generator/checker 48, the BCC register 33, the end code decoders 52 and 35, and the U~RT multiplexor 27x.
~he ~ertical parity generator/checker.48 generates odd parity for every word transferred by the LCP over to the Main System 10. ~he generator/checker 48also checks for odd 9g _ ;,;, ~ ! ~
r ~

pa~ity of every word trans~err~d from the ~lain System over ~o the LCP. Each word to b0 transferred from the particular L~P over to the Main System lO is first placed in the 17~bit register called t,he data latch register 49. The data latch register 49 then transfers' the word over to the Main System lO. m e use of the data latch register increases the rate ,, of data transfer by allowing quicker access to data s-tored in the LCP RAM buf,fer 25 ~The longitudinal parity word (LPW) register 24 is made lO of 16 separate flip-flops operated in the "toggle" mode. It.
; receives its inputs from the terminal bus 47. When the Main Syste~ lO sen~s a Command Descriptor ~/D, a Descriptor Link D/L~ or data, o~er to the LCP, the LPW register 24W accumulates ~~
a LPW (longitudinal parity word) to be ehecked against an 1~ LPW from the System 10~ When the LCP sends data or a Result Descriptor R/D over to the System 10, the LPW register 24 also accu~latesan LPW to he sen~ to ~he System 10 Acc~mulation of the LP~ consists of applying each word being sent or recei~-ed to t~e input of the LPW register 24W and ' performing a binary addition without carry (exclusive OR
~unctio~).
Yhe LPW register ~.4~ is~initiali~ed to "all ones" prior to each operation in which an LPW will be accumulated in the LPW
register. At the end o~ a data transfer from the Main System 10, the e~clusive OR fun.ction is performed between the accumuLated LPW andan LPW from the System 1O. IE no errors ha~e occurred) both L~W's will be identical and the resultant value in the LPW register 24W will be ~all æeros".

.
`!

`$

In FIG. 6D the end code decoders 52 and 35 are used to determine the receip-t of ~ ending code character. Decoder 52 h~ndles the ~B digits ~nd decodsr 35 hanAles -the CD
digit~ The ~B d_git end-code decoder 52 i3 used to identify an ending code in the first character position of a word from the Main System. This decoder'is also used to identify an ending code in any character sent from the terminal unit deYice interface 22di. If decoder 52 receives such an ending code, it causeq the le~el EDCODE and the levsl SYSEND
to be gener~ted. ~he CD digit decoder 35 is used to identify an ending code in the last character position of a word from the System. ~eceipt of s~sh an ending code by decoder 35 will cause the ~oltage le~el SYS~D to be gener~ted.
T~a abo~e discussion inY~olved the second section B of the LCP. Now t~e third section C, the System ~ogic Section ; of the LCP,will be discussed with re~erence to FI&. 6D~
The Status Count Register 53 ~STC) is a four-bit register. ~his register develops 5tatus Count le~els (STCnL3 for use in the LCP and le~els designated LCSTUn (~5P Status Le~els) for transmission to the ~ain System 10. In conjunction with providlng floatîng logic le~els, the STC
register 53 also controls the seq~lencing of opera-tions ~or the LCP. Each Status Count developed by the STC register 53 ~pecifies a different phase of operation in th~ ~xecution , 25 of a Command Descriptor ~/D~ as wa~ previously outlined in t connection with FIG. 6A. The decoder 54 i5 a binary coded decimal (BCD) *o decimal decodelP which changes the BCD
qalues o~ the STC register 53 to decimal values required by the LCP systemO
.

Reference t~ FIG. 6E will be instructive in r~iewing the system in-terrelationships between the ma3or LCP elem~nts invQlved in regard to the logic and control signals operating between these elements. FIG. ~E shows the major logic a~d control lines between the IOT (Input-Output Translator) lO
the Distribution Card 20 d (for the Base Module 200)~ the particular Line Control Processor LCP 20 and the peripheral terminal unit 50.
~ First re~erring to *he lowe~most g~oup of control lines, the LCP 2000 and its Di~tribution Card 200d~ the designation LCP~EQ (n) is a group of eight "request" Iines where the letter "n" represents ~hs numbers 0-7 for each specific ~CP
in the Base Module 20 . Each of these signals is driven by one particular LCP over to the Distribution Card 200d~
1~ signa1 is used by a particular LCP to "re~uest1' a connection to the System lO and cau~e3 the Distribution Card 20 d to ~et llp a "Poll Requestn.
The next designation LCPCON is the designation ~or "LCP
connectedn. This line is driven by the connected LCP (0-7) to the Distri~ution Card 200d~ This signal i~ driven by the LCP when it detects its own particular LCP address and it is not in an "off-line" condition. The signal i9 a re3ponse to the LCP address and ~ignifies to the Distribution Card 200d the pre~ence of the LC~ addressed.
The designation LCPSTL signifies "LCP Strobe Level".
Thi~ line i3 driven by tha "connected" LCP over to the Distribution Card. It is the particular LCP's designation of "send" or "acknowledge", depending cn the data direction involved.

:{

, - 102 .. ~.. . _ . . .

The IOSND designates I/O send. This line is driven by the "connected" LCP to the Distribution Car~ 200d.
This lines defines the direction of the bidirectional data lines marked D~.TA (xn)O When this line is active low, the data lines will be driven by the Distribution Card 20 d to - the ~ain System 10 via IOT lOt.
The LCSTU (n) designates the status of the particular LCP where 'Inll may designate either of LCP's 0-7. This line is-driven by the particularly-connected LCP to the Distribution Card 200d and reveals the "status" of the LGP as shown in FI&. 6A
Referring ~o ~IG. 6E, a number of connections ~re provided as between the LCP, such as 20 and the Distribution Card 2~ d The DATA (~Yn) represents the "message level interface" (as previously shown in ~IGo 5E of which the lower 16 lines are the data lines for the digits ABCD). The next higher line is the PARI'~Y line which carries the parity bits. These 17 lines constitute the message level interface and are of a bidirectional nature, that ls to say, transmission j 20 may occur in either direction along these lines depending on ¦ the logic control lines used to determine the direction of 'i transDlission.
i ` The designation E~EQ in FIG. 6E signifies the ;~ "emergency request" line. This line is driven by one or more ! 25 LCPs to the Distribution Cards. The LCP may drive the emergency request line at any time. The elllergency request signifies thatan LCP nee~s system access quickly to avoid a t dat~ transfer failure. Only-LCP's wnose lack of system access will necessitate operator intervention or difficult . i :

.. .

error recovery~ will drive the emergency request in conjunction with their LCP r~quest. Those LCPs which are not emergency requesting, will disable their ~CP rsquest wlth this line. A Distribution Card detecting an emergency request, will cause a Global Priority of ~seven" to be transmitted to the Main System 10 during a "Poll Request".
The designation TER~ in FIG. 6E designates a "terminate"
voltage level. This is generated on a Distribution Card and i~ s'ent to the LCP to terminate or end an operation.
The designation LCPAD "n" in FIG. 6E designates the LCP address (where "n" can be 0-7) to designate the indi~idual LCPs. Ona of the~e eight ~ignal lines is driven by the Distribution Card to each particular LCP. The receiver in the LCP will be jumpered to the proper line.
Thi9 3ignal is functionally a connection line to the LCP.
An'~CP receiving its LCP address is "connected" to the Main Syst~m 10 through the Distribution Card.
~ The STIOL in FIG. 6E si~ni~ies the "Strobe I/O Leveln.
I This line is driven by the ronnected Distribution Card. It represents the Sy~tem's "send" or "acknowledge" depending on th~ data direction.
,. The A~QOUT line of FIG. 6E i9 the output end of the Di'stributlon Ca'rd which has an input designated ARQIN. These represent "access request in" and "access request out".
t 25 These signals are driven and recelved ~y Distribution Cards only and consist of short line's between adjacent Distribution Cards. They are used during nPoll Test~' to re~olve Distribution Card priority. The lines DC--' t~ and the D~,B 2 .
I represent Di~trlbution Card ~'busy9' levels '{hese are O

, , 104 _ %

generated on each actiYe Dist~ibution Card in a Base Module to xesol~e ~istribution Card Pxiorit~ in the module during a "Poll Request" s~quence.
The PTALB line designates "Poll Test active level".
This is a ~idirectional ~ignal le~el between Distribution Cards in ~he same Base Module. ~ Distribution Card perform~
ing a "Poll Test" o~e~ation sends this level to the other Distribution Caxds, thus inhib.it~ng them ~rom conducting a "Poll Test" or a "Poll Request" seguence.
Each Base Module may ser~ice not onl~ one "main system"
10 ~ia its Distribution Card C20Od,FIG.2~ but may be provid~
ed ~ith multiple Distràbution Cards to cooperate with and sexvice other host "main systems". Each Distribution Card in a Base Moaule can service a di~ferent host system and each host system ~ould follo~ the same basic organization shown in FIG.3.
` The REQACC làne designates "Request Access"~ This line is dri~en by and xecei~ed by Distribution Cards only.The line is used to signi~y an interrupt request as being "active" by the Distri~ution Cards.
The BUSY line of FIG.6E designates a Base Module "~usy"
~ le~el, This is a hidirectional signal level developed on a ! Distribution Card ~hen that card has made a "connection" with the Main System 10. The level is sent to other Distribution Cards on the same Base Module to indicate tha~ the LCP
backplane is in use.
Now ~urther in re~erence to FIG.6E, the relationships ~etween the IOT 10t and the Distribution Card 20Od will be discussed. ~t the upper left of FIG. 6E, the LCPST designat;
es the LCP Stro~e Pulse. This is generated on a Distribution Card from the LCP strobe level and is sent on to the ~ain - System via the IOT 10t.
~ he PB~ST ~ designates "Port Bus~" or the LCP status 2 line, This line xesides on the mes~age level inter~ace as shown in FIG. 5E. In the ~unconnected" sk~e thi~ lin~

: ( ) ) indicates a Port ~usy condition during a "~oll Te~t"
- algorithmO In the "connected state", this line ca~ies bit 2 o~ the LCP's status to -the Syste~ 10.
- The IP/ST 4 designates an Interxupt Reque~t or a Poll Test parity error, or an LCP status 4 line. In the unconnected state, this line is used to carry an"Interrupt Request" from the LCP or else to indicate ~n address parity error during a "Poll Test" connection attempt. A~n Interrupt Re~u-est indicates that~ LCP is requesting acces~ to Memory.
In the nconnected" state, this line carries bit 4 of the - L~P's status to the Main System.
Ihe E~/ST 8 designates "emergency request" or the LCP
~tatus 8 lineA In the "unconnected" state, this line re~resents an emergenoy re~uest from the LCPA ~Emergency 1~ request" desi~ates that an LCP needs immediate access to the Main System. In the "conn~cted'r state, this line carries bit 8 o~ the LCPs status to the Main System. Once connected, the LCP indica-tes its System Memory requirements by its status. The LC~ status is gate~ c~ntinuously and may only be considered ~alid by the System at LCP "Send/Acknowledge~
time.
- Further in FIG. 6E to the connections between the IOT
10~ a~d the Distribution Card 200d~ the conneetions designated ~ PARITY and DATA "xn" refer to the message l~vel interface ; 25 lines previously discussed. The CS/ST 1 desi~nates ~Channel Select" or LCP status 1 line. In the "unconnected" state, this lines carries "Channel Select" from the System 10 to the Distribution Card. ~Channel Select" i5 used in conJunction with ~address select" in both connection algorithms.
'~` , ' , ' ~
. ~ , .
. , 106 _ , . .. ... , ............................................................... :

Howe~er, in the 1'colmected" state 9 this line carries bit 1 of *he LCP's status to the Main System 10. This line is a bidirectional line. The recei~er on the Distribution Card will be any standard TTL ~e~rice. The driver on the Distribution Card will be a tri-state driver such as a 8097/
8098 (Na~ional~Semiconductor Corp.) or equi~a~ent which will be acti~e only in the connected state.
The TRM designates the ;'terminate" level. This is sent from the Main System 10 to a Distribution Card when a da*a transfer operation is to be terminated.
The ADDSEL line of ~IG. 6~ designates "address select".
This signal line indicates that the Main Syst~m is connected or is attempting co~lection to a specific LCP. This line is ` used in conjunction with "Channel Select" for both connection algorit~ns to achieve connection~ Once a connection to the LCP is achieved, the System and LCP remain connected until the signal line is inactivated by the System. When the line i9 acti~e, the System can be considered 7'busy".
Again referring to FIG. 6E, the AG/SIO designates "access granted" or "Strobe I/O". When the interface is in an nunconnected state", this line carries an "access granted"
signal. "~ccess- granted" is used to ackno~ledge an Interrupt Request for connection and to be~in a "Poll Request"
àlgorithm. With the interface in a "connected" state, this line carries a "Strobe I/O" signal. This slgnal is the System's Send/Acknowledge line in transferring information between the System 10 and the LCP Base Module. The actual sig~al is a 100 nanosecond minim~un pulse sent ~rom the ;. .
System and latched by the Dtstrib~tlon Card~ The Distribution _ :L07 -.. "~ ~ .. ...... ~ ..... . . .

~ard will ~eneraily clip the first 50 nanosecond~ from the signal to allow for cable settling time.
I~ regar~ to FIG. 6E 9 the control signals as between the L~P 2000 and the peripheral -terminaL ~nit 50 indicate a line designated ~D~TLN. Tl~is designates Remote Data Line Level. This is a bidirectional signal level which permits the transfer of serial data between the LCP a~d the peripheral terminal unit in one direction or the other direction as determined by the level.
Discussed ~ere and below are the operational se~uences of the LCP. The logic terms are referred to as either bein2 a~ti~e or inacti~e in order to avoid any ambiguity that might result fsom using the terms True and False.
Receipt of Instructi~¢~ ine Control Processor:
Previously in ~IG. 6A, the logic flow invol~ing the Status Counts (STC~ between the LCP 20 0 and the Main System 10 was di~cussed. Now re~erring to FIG, 7A there will be seen in greater detail a simplified flow diagram illustrating the receipt of instructions by the LCP. ~his flow chart show~ the basic actions of the LCP during receipt o~ `~
instructions and also shows those actions which can occur due to modification of the original instructions, the receipt ~f a time-out level, and the occurrenoe of error condition~.
` Prior to recel~ing any o~ the se~e~ possible instructions ~! 25 from the Main Sy~tem 10, the LCP is normally in an "idle"
`~i state at Status Count 3. Howe~er, the LCP can also be in a STC 3 during a "Read" operation, awaitlng either a conditional cancel instruction from the Main System 10, or a data transmission from the peripheral terminal unit, such as ` 3 50.

... .
., .

; - 108 ~

The following will ~escribe the actions o~' ~he ~CP
during receipt of instructions from the Syst~m 10 ~i~ during prepar~tion for the ins:truction execution. These actions - are itemized as (a), (b), and (c).
(a) S~Jstem LCP connection~ with the LCP in STC 3, the Syste~ makes a connection with the LCP throug~l a Poll Test"
sequence, and -the LCP receives its unique address level (I~PAD) (n)~ as was illustrated in FI&. 6E. The receipt of LCPAD (n) causes the LCP to send the LCP connection le~el (L~CON, F~G. 6E) to the associated Distribut-on Card 200d and generates LCPADL (LCP Address ~evel), which "enables"
portions of the LCP syste~ logic section. The ~ddress level LCPAD (n) also enables the DCP bac~plane ne-twork by generating a gate system level (GATSYS). Then a strobe (STIOL) is received from the Dis-tribution Card (20 d~ FIG. 6E) causing S~IO~ ynchronous Strobe Flip-Elop) to be ~et. The settin~
~ STIOF activatesthedesired module of the LCP by setting RECVF ~Re~eive ~lip-Flop~, enables setting of the LPW
r~gister (24 , FIG. 6D) to logic "l'sn, and sets selected flip-flops to a beginning state. The Command Descriptor C/~
~9 received in the LCP and is loaded into the OP code register ; 42 ~nd variant registers 43 (~IGo 6D3. Receipt of the C/D
res~lts in ~n ~P~,~ being placed into the L~W register 24 .
The C/D is checked ~or validit~ and the valid OP flip-flop (~'OP~) is set. The LCP then steps from STC 3 over to STC 11 (FIG. 7A) to recei~ean LPW from the System 10.
(b) Receipt of LPW by the LCP: In FXG. 7A at STC ll, a longttudinal parity word (LPW)is receivçd from the System 10 and is checked again~t the contents of ~he LPW register iJ ( - lO9 _ 24W to validate lon~itudinal pa~it~ o~ the C/D transfe~.
Vertical pa~it~ is ~lso checked, then a vertical level OK
CVLOK1 and,vertical paxit~ OK level ~VPAROKI is set. The LCP bu~er address is preset ~o 253 in the memory address ~esistex MADR 36 ~IG.6D~, and setting o~ the LPW register 24W to logic "l's" is again enabled; then the LCP steps to STC 6 to xeceive the Descriptor Link D~L from the System 10.
Ccl Receipt o~ Descriptor ~ink and Descriptor Link LP~:
at STC 6, the,LCP receives the two words of the Descriptor hink DfL ~rom the System 10 and an LPW is accumulated in the LPW register 24w. An hP~ is then recei~ed from ~he System 10 and is checked again~t the contents of the LPW register 24w.
. ~he Descriptor Link D~L and ~he LPW are stored in buffer address locations speci~ied b~ the memory address register . MADR 36 as addresses 253, 2~4 and 25S ~IG.6C~. From STC 6, ~, ~ the hCP branches to STC 8 ~or a "~rite" operation, or to STC
1 or a "~ead" operation, or to STC 7 if a Descriptox Link ` `I erxor occurxed.
There are alternate ~low path situations such as:~a~
~hen a "conditional cancel" instruc~ion is recei~ed from the ~ystem 10, or 0b~ a data transmission is recei~ed from the pexipheral terminal unit, such as 50, or ~ a time-out j le~el is generated~ or Cd2 a receipt of test instructions~
To ~urther ampli~y these alternate flow path situations per FIG. 7A: ~a~ Receipt o Conditional Cancel instruction: at : STC 3, if a conditional cancel instruction is received from the System 10, while the LCP.is awaiting a ,ransmission from the perip~exal terminal unit 50, a cancel flip~flop ~CANCF) is set an~ the LCP steps-to:STC ll tM~receive a Command Descriptor longitudinal parity word, LPW~ From STC 11, the ~ 110 -J `~ . `

fi`~

LCP steps io ST~ 7 and sends a Result Descriptor to the - System 10, indicating that th~ cancel operztion i3 completed.
. ~b~ Receipt Qf Transmission from t~e Peripheral Ter~inal Uni~:
-.- at STC 3 during a "Rea~" operation~ if -the termin2.1 busy ~lip-flop (IRM3SYF) is set, indicating that terminal unit has starte~ transmitting, the LCP steps to STC 1 to receive data from the peripheral terminal unit. Th9 LCP continues to recei~e data and completes the remainder of the Read operation in accordance with instructions contained in *he Command Descriptor C/D.
(c) P~eceipt of Time-Out Level: during ~ "Read" operation, with the LCP in STC 3 awaiting a transmission from the peripheral term~nal unit (and i~ the l-second timer is not inhibited) then if there ii a l-second delay in receiving ~he transmission, the time-out level 1TIMOUTL) is generated.
With TIMOUTL acti~e, the end flip-flop (ENDF) i.s set, the terminal complete (q~iCNP~ le~el is generated, and the LCP
steps to STC 1. At STC 1 a request for reconnection to the System is initiated and the LCP stsps to STC 5, ~IGo ~B.
20 ` At STC 5 with ENDF set, the Read operation is terminatsd and the LCP steps to STC 7 to send a Result Descriptorl R/D, to the System 10. A time-out level can also be received wit~
' the LCP at STC 1.
`' (d) Receipt of Test Instructions: at STC ll, FIG~ 7A7i~
TESTF (Test Flip-Flop) is set indicating that a test instruction was raceived, the LCP completes the test operation by ~tepping to STC 7 and sending a Result Descriptor R/D to the System 10.

.
` ~ ' ' o~

6~

Error Conditions: the occurrence OI` two typas of error conditions (ea~ and (eb) during the receipt of in~trUctiQns will be acted upon b~ the LCP, a~ follows: (ea~ Command De~criptor parity error: 3:n FIG. 7A, at STC 11, if the VLOE (Validity Level OE) level is not acti~e, or if VOPF
(Valid Operation ~lip-~lop) is not se*, the LCP steps to : STC 7 to send a Re~ult Descriptor R/D containing a descriptor error to the System; (eb) Descriptor Link parity error: at STC Ç~ if the VLOK level is not acti~e9 the LCP
steps to STC 7 to send a Result Descriptor R/D containing a De~criptor Link error to the System 10 Write Operation: .
i Referring to FI~. 7B, there is seen a sequential logic diagram which is ~implified to show the ~teps invol~ed in the - nWrite" operation. Let us assume that one buffer load of data will be transferred from the Systam 10 to the peripheral tarminal unit 50, followed by a partial buffer of data .~ containing an endi~g code character in the last character I position ~CD digits~ of a wnrd~
`. 2~ The following steps (a through i) describe actions of ~ the LCP, such as 200o, during transfer of dzta from the I Sy~tem 10 over to the LCP1 and from the TCP to the pe~ipheral terminal unit, su~h a~ 50.
¦ (a) Receipt of data from sy~tem: at STC 6, if a "Write"
operatio~ is spe~ified by the Co~mand Descriptor C/D, the LCP enables the etting of the LPW register 24W to logic s~ then steps to STC 8 to r~eceive data from the System 10.
An IOSF (If'O Send Flip-Flop~ is used and put in a reset state at ~ time to enable the bidirectional data lines . ~

` ` ~ '' `~

for transf~r of dat~ ~rom the Syste~ 10 o-~er to the LCP.
Ther~ are provided multiplexor control le~els SL~ (Select A Input Multiplexor) and SL~N (Select B Input ~ultiplexo~).
These are both inactive, connectin~ the data lines to the . 5 input multiple~Yor network 24 1 ~ ~I&S/ 6B and 6D. T~:re are other multiple~or control levels SLARU~I (Select A Level Terminal Bus Multiple~or) and SLB~ (Terminal Bus Multiple~or Select B Level). These also are both inacti~e, connecting the input multiplexor network 24Xl to the input of the Terminal Bus Multiplexor Network 24 2~
At STC 8~ the Receive ~lip-~lop (RECYF) is set, activating ~e writ2 module o~ the LCP. The setting of ~ECVF causes the write enable level ~ESYS~ for the ~CP buffer to be active.
Thus, data is transferred from system Main Memory 10 over to the ~CP buffer 2500, o~e ~ord at a time, by way of the terminal bus 47 of the T,Cp. An Asynchronous Strobe (STIOL) ; from the associated Distribution Card 20~d (FIG~ 6E) accompanies the transfer of each word, and as each word is received by the LCY~ the W P sends a strobe le~el (LCPSTL) to the System 10 to "acknowledge" receipt of the word. As each ~ord is piaced on the terminal bus 47,then~ in.addltion to being sent to the buffer 250o,it is also applied to the input o~ the ~Jertical parity generator/~hecker 48, the LPW
register 24W and the end code decoders 52 and 35. Yertical 2~ -parity is checked and a longitudinal parity word is accumulated in the LPW register 24w. Transfer of words continues until the next to last data word address 251 is attained in the Memory Add~s~ Register 36. ~he LCP then ~` steps to STC 10 of FIG. ~B to receive one final word from .

_ 113 -~ ` :

2~

the System. At STC 10, the LCP rec~ives the fi~lal word to ~fill the buffer, and then steps to STC 12 to receivean LPW
from the System 10.
(b) Receipt of LPW and disconnect from the System 10:
at STC 127 the LCP receives~n LPW from the System 10 and chec~s it against the LPW acoumulated in the LPW regi~ter 24W during the data transfer. The LCP then enables setting of the LPW register 24 to logic "1 t S~ and steps to its STC 1, disconneoting from the System 10 in order to transfer data to the peripheral terminal unit, such as 50. Terminal bus multiplexor oontrol levels SLARAM and S~BRU~M (Select A
` and Select B of 24x2) are both inactive thus to connect the ; output of the buffer 2500 with th~ input to the terminal bus multiple~or network 24 2. The input multiplexor 2~ z has control leYels SLAIN (Input Multiple~or Select A Level) and SLBIN (Input Multiplexor Select ~ Level) which will be ~ controlled during the data transfer by the state of the even i. flip-flop (EVNF) in order to access a character alternately from the AB digits and the CD digits of a word Ln the buffer . 20 2500-~c) Transfer of Data to Peripheral Terminal Unit; with ~ further reference to FIG. 7Bg at STC 1, the receive flip-flop i (R~CVF) is reset, thus enabling the recei~e module of the LCP.
The terminal start level (TE~ST) is generated to prepare the t 25 LCP for operation with the peripheral terminal un~t. The ~ TERST level enables the setting of master clear UART flip-, .
flop (~CUARTF) in order to clear the UART 31 (FIG. ~D~.
The ~etting of a terminal active flip- M op (T~ACTF)~ a send flip-flop (SEND~), and the terminal busy flip flop (IR~SYF) :, ' ~

~ ~.

~ ' `i ."'' , . ~ ' ' .
ar~ alsb enabled~ activatlng ter~inal coIltrol logic fcr a Write operation and specifying that the peripher~l tcrminal u~it is in a "busy~ state, The Memol~ Address Register 36 (FIG. 6D) is set to ~ ~ 1 0 to access the first ~rord in the buffer 25 . In the U~RT 31, the tran~mitter holding register empty (T~RE) level is acti~e, and the setting of the UART empty flip-flop (U~RTET~') is enabled to provide a strobe level to the ~ART mul-tiplexor 27X~
~e UART 31 accepts one character at a time from the LCP buffer 2500. The e~en flip-flop (EV~F) is used in conjunction with the Memory Address Register 36 to control accessing of characters. ~hen loaded with a character, the UART 31 transfers the character serially o~er to the peripheral terminal unit, such as 50~ As each character from the buf~er 2.500 i5 placed on the terminal bus 47~ it i~ also applied ta i the input of the block chècX character re~ister ~BCCR) 33, ; ~hich (after a STX/SOH,'Istart o~ test/start of heading"
character has been received) beginY to accl~mulate a blo~k check c~racter during the data transfer. The UART 31 continues to accept character~ from ~he bu~fer 2500 7 then transferring them to the peripheral terminal unit 50, unt;
memory addres~ level MADR ~52 is attained in the Memory ~ddress R2gister 36, indicating that the last word in the buffer has been accessed.
(d) Request for Reconnection to System 10: the mamory address le~rel MADR 252 causes t~e buffer transfer flip-flop (33EXFRF) to be set, indicating that the buf~er 25 Deeds s0rY~'ce, and the LCP initiates a re~uest for reconnection to the Sy~tem by enabling the setting of the LCP request flip-flop LCPRQF. l~le setting of IOSF (I~O Send Flip-Flop which - ~Idicates the direction of data flow on the message le~el in$erface) is enabled to condition ~he data lines for transfer o~ data to the System 10, and the setting of ~DR
253 level is enabled to allow acces~ to the Descriptor Link D/L (F~G. 6C). ~he LCP then steps to STC 5 of FIG. 7k to ~end the Descriptor Link D/L to the System 10. There are floating logic levels which genera-te LCP~DL (LCP Address Level) when the LCP address le~els (0-73, LCPADn, is received from the associated Distribution Card during the reconnection sequence 9 and the LCP generates a le~el called gate system ,; (GATSYS) to enable the backplane network. The level LCP
~, .
~ connected (LCPCON~ is sent to the Distribution ~ard 200d to . . .
indicate that the LCP is connected.
- 15 (e) Transfer of Descriptor ~ink and the Descriptor Liik LPW: in ~IG. 7B, at S'~C 5, the transmit flip-flop ~ (XMIT~) is set, activating the "Read~ module of the LCP.
`~` ~h2 LCP trans~ers the Descriptor LinX D/L and the LPW
(pre~iously recei~ed ~t STC 6) back to the System 10. '~he LCP enables the setting o~ the LPW register 24 to logic nl~sn ~7~d if the Ma~n System has.more data to send,~the LCP ~ep~
again t~ STC 8 to receive additional data rom the System 10.
(~ Receipt of Addltional Data a~d ~nding Code ~r~m System 10: at STC 8~ the actions of tha LCP ~ile receiving the "second" buffer load of data from the Syste~ 10 are t~e same as those per~ormed during receipt of the first buffer load~ ~p to the point that a~l ~ending code~' is reco-gnized by t~e terminal ~U5 47. When an "ending code" in the l~st character position (CD digits) of a word is placed on the ' .

- _ _ terminal bus 47~ then a system end ]e~el (SY~END) is - generated. SYSEND level causes ~ne data input for the end-flag 25e of FIG. 6C (RAM 18 L) to be active and the en~-flag bit ~ENDFG) and the ending code char~cter are both stored in the current buffer address. The TCP then steps to STC 12 to receive an LPW from the System 10.
(g) Receipt of LPW and Disconnect ~rom System 10: at STC 12 of ~IG. 7B, the LCP receives the longitudinal pa~ity wor~ LPW and checks it against the LPW accumulated in the LPW register 24w. The LCP then steps to STC 1, disconnec~ing from the System 10) to transfer the remainlng dat~ and the ; endin~ code to the peripheral terminal unit.
(h) Transfer of Data and Ending Code to Peripheral T~rminal Unit: at STC 1, the actions in transferrinO the remaining data to the~peripheral terminal unit are the same a~ those performed during transfer of the first buffer load, up to the point that an ~ending code" is recognized on the terminal bus 47. When an ending code is placed on a terminal ~, bus 47 ~rom the output of the buffer 25 , the ending code i~ transferred and th~ end ~lip-flop (ENDF) is set. The accumulated block check character in the BCCR 33 (if a BCC
1 1~ being generated) is then trans~erred to the peripheral ¦ terminal unit such as 50. SENDF (~end flip-flop) and TRECF
' (terminal receive flip~flop) are both in a reset state, -~ 25 causing terminal complete (IMCMP) leYel to be acti~e. The terminal complete le~el causes the LCP to initiate a re~uest for co~neotion to the System 10~
Request for Reconnection to Terminate Write Operation: the LCP requests a reconnection to the System by ena~ling the set-ting of LCP~QF (LCP Request Flip-k'lopJ~ ln conjunction with the reconTlection, the LCP steps to STC 5 - of FIG. 7B, sends the Descriptor Link D/L to t~le System 10 and then steps to STC 7 to send a Result Descriptor R/D to the System 10.:
The abo~e discussion completes the explanation of the general flow path for a ~Write" operation in which more than ~ one buffer load of data was transfPrred, and in which the .. operation was concluded ~y receipt of an "ending.coden.
This describes the normal situation~ Xowever, there could : be alternate flow paths and possible error conditions which ~ight occur as ~ollows, in reference to ~IG. 7B. The following items ~a~ t~rou~h (c) describe the actions of the LCP when modi~ications" to the original Write instructions are madé
by the System 10 or the LCP.
(a) Request for Em~rgency Access to System 10: during transfer of data from the LCP to ~he peripheral terminal unit 50, when the LCP buffer 2500 is oompletely empty, a flip-~lop B~XFRE' is set. ~his is the buffer transfer ~lip-flop ~ which is located on the Terminal Card; this flip-flop is set when the LCP buffer i5 filled with data from the terminal ~nit, ol~ when emptied of d~ta during trans~er of data from t~e ~CP to the peripheral terminal unit. When BFXFR~ is set~ this enables the setting of LCPRQF (LCP Request Flip - ~lop, whic~, when set, indicates th~t the ~CP requires access to the Main System Memor~ lOm), The setting of the LCPRQF initiates a request for r~connection to the System 10 to either send data to the Main.System or to obtain more data if tne buffer is empty. If a reconnection is not campleted prior to the time the transmitter-holding register of the .

UART 31 is ready to acoep-t another character, the LCP causes the emergency rsquest level (EMRR~Q) to be gellerated. The E~D~REQ level is sent to the acsociated Distribution Card 200d ~o initiate an emergency request for recoI~lection to the systen~.
(b) Receipt of Ending Code ~AR digits): if an ending code is identified in the first character posi.tion (AB digits) of a word from the System 1.0, then EDCOD~ (end code level~
is generated. EDCODE is generated on the terminal contro~
card when an end code character is .in the A and ~ digits of the te~ninal bus 47. Also generated is SYSEND (System End Code T~e~el~. ~hen active, th.e SYSEND level indicates that an end code character is on the terminal bus 47. At STC 8, the EDCODE level enables the setting of a character end flip-flop (CHA~ENF), and the SYSEND level genera'es the 18th bit Write end-flag level,RAM 18L~ The "Write" end flag le~el is generated on the te~ninal control card from the EDCODE level; this is the data input level for the end-flag RAM of the LCP buffer 2; O.
The ending code and the ENDFG (end-flag level is generated ` 20 on the data flow card from RAM 18 L; ~hen active, this level :~ identifies the address of an end-code in the LCP buffer) ars stored in the current buffer address of the LCY, and the LCP
ste~s over to STC 12 (EIG. 7~) to receive a longltudinal parity word LPW. At STC 12, the LCP receives an LPW from - 25 the System 10 and checks it against the accumulated LPW in th~_LP.~_.register 24_.. _The LCP then_steps.to._SIC_~. to .
initiate decrementing of the System Memory Address. (The address must be decremented by two digits to accurately reflect the address of the ending code in System Memo~).

.. . ... . , , " , . ...

,~ r ;' ' .

. ~rom STC 9, the l,CP steps over to STC 1 to t~s~r data `~ ~nd the ending code to the peripheral te~inal unit 50.
.. At STC 1, recognition o the ending code on the terminal b~s 47 causcs t~le LCP to perform the same actions described during the previous "Writ~" operation at STC 1 when data9 ending code, and bloc~ check characters are trans~erred to the peripheral terminal unit 509after which the LCP disconnects from terminal uni~ 50 and reconnects ~o the System 10 and terminates the "Write" operation.
(c~ Receipt of Terminate Signal from System 10: a .; te~minate signal (TE~ level9 FIGS~ 6C, 6E)i.s sent ~rom the . Sys-tem 10 to the ~P ~-henever System Me~orv space designated ~or ICP operation is to be exceeded~ During a nWrite"
operation, the TE~M level can be received at STC 8, STC 10, or STC 12, FIG. 7B. The actions of the ~CP upon receipt of tha TERM leYel (Terminate Level) depend upon the Status Count -in which the LCP is operating, and upon whether or not the receipt of TER~I level is preceded by a receipt o~ an "ending code~ from the System as follows:
(1) Receipt of Terminate Signal Before Ending Code:
i~ the T~RM level is received at S~C 8 or STC 10, the LCP
steps o~er to STC 14. At STC 14, regardless of whether l~I
leYel remains acti~e or is now inactiYe, the LCP steps over to STC 12, receives and checks a longitudinal parity word LPW, then steps,over to STC 7 to send a Result Descriptor R/D to the System 10. If an ending eode is received in the CD digits (last charac~er) o~ a word at 5TC 8 or STC 10, and the TERM level is also received, the I.GP steps to STC lLi.
At the S~C 14, if the TERM level i~ qtill acti~e, the ending . ~r............................... - ~20 -, " ~ .

code was not placed in the LCP buffer 250~. The LCP t~en steps to STC 1?~ recei~es and checksan T PW~ then steps o~er ` ~o STr, 7 to send a Result Descriptor R/D to the Sys tem 10.
(2) Receipt of Tarminate Signal After ~ndirlg Code^
i~ an ending code is recei~ed in the CD digits of a ~ord at SIC 8 or STC 10, the LCP ~teps to STC 12 to receive LPW. At STC 12, if the TERM le~el i~ now received, the snding code is transferred to the LCP buffer 2500 and the ~CP steps orer~to STC 1 to transfsr remainin~ data and the ending.code . 10 t~ the per-pheral terminal unit 50. At STC 1, recognition .~ of the ending code on the term.inal bus 47 causes E~DF to be ~et. ~End flip flop: when set) th-C f~ip-flop indicates that the terminal contro$ section o~ the LCP has ended its operation).
The setting o~ E~DF indica.tes that there is no more data to be transferred; after the data, ending code, and block check character are transferred to the peripheral terminal unit 50, the ~P disconnects from terminal 50 9 reconnects to the Sy~tem 1~, to terminate the "Wri-te" operation~ .
~ As illu~trated hereinunder~ at STC 1, the recognition `' of the ending code on the terminal bus 47 causes t~e ENDF
~end flip-flop) to be set. The setting o~ ENDF indicates i that there is no more data to be transferred; after t~e data, ending code and block check character are transferred to the peripheral terminal unit 50, the LCP reconnects to the System 10 to terminate the 'iWrite" operation.
an ending code i9 received in the AB digits of a ~ word at STC 8 or STC 107 and the TE~M level is also receired, `~ the LCP steps to STC 14. At STC 1~ 9 if TERM level is .inactivo, the who3e word containing the ending code in the -.
.

~s .,.. ,_.~,.. ,_, . ... .

~,.f.~ q",f.~
`: ~

- AB digit was transferred to the LCP buffer 2500. A correction of System Memory Address is necessary. f~le LCP steps to STC 12, receives and checks the LPW, then steps to STC 9 to initiate decremen~ing of the System l~emory Addre~s. I~e LCP
then steps to STC 1 to transfer data and ending code to the peripheral terminal unit 50.
~`~ If the TE~M level was still active at S~C 14, then only the ending code character was transferred to the LCP buffer 2500 and no correction of System Memory Address is required.
The LCP steps to STC 12, recei~es and checks the EPW, then steps directly to S~C 1 to transfer data and the ending code o~er to the peripheral terminal unit 50.
Error Conditions: During a "Write" operation the following error conditions (a,b,c,d) will be acted upon by the LCP:
(a) Access Error: after transmitting EMRREQ le~el to the associated Distribution Card, if the LCP does not receive a reconnection to the System 10 prio-r to the time the UART 31 is completely empty, the LCP enables the setting o~ the access error flip-flop (ACCERF). The setting o~ ACCERF
enables setting of the end flip-flop (ENDF), and the LCP
initiates a request for reconnection to the System 10 to terminate the "Write'7 operation and to sen~ an error Result Descriptor R/D to the System 10.
(b) System ~ertical Parity Error: during transfer of data from the System 10 to the LCP, if the vertical parity is--not-~ and---the-VPAROK_leve-l-is_not_ac~iY~_a~te~_~ac~ _ check ~ vertical parity, then the vertical parity error --~22 .

`:
flip-fLop tVPERF) i5 ~et to indicate the existence of a ~ertical parity error. l~e absence of VPAROK level also ; pre~e~ts the vertical longi-tudinal OK level (VLOK) from being gensrated~ and at STC 12, the LCP step3 over to STC 7 to send an error Result Descriptor R/D to the System 10~
(c) Longitudinal Parity Error (FIG. 7B): when the longitudinal parity word is checked after a data transfer ~rom the ~ystem 10 to the LCP, if longitudinal parity OE
level ~LPOE) is not acti~e, the longitudinal parity error flip-flop ~LPERF) is ~et to indicat~ existence o~ a longitudina~ parlt~ error. The absence of L~WOK level (the LPW ~E level: is generated on the data flow card fro~ the terminal bus 47 le~els; when active, it indioates to the System Logic Section of the LCP that the ItPW i~ correct3 prevent VLOX leYel from being generated, and at STC 12, the t W P steps over to STC 7 to ~end an error Result Descriptor R/D to the System 10.
(d) Terminal Vertical Parity Error: during transfer of data from the LCP b~ffer 2500 to the UART 31, if the ~ 20 vertical parity 0~ (VPAROK) level does not remai~ acti~e ', for each character transferred, the termin~l vertical parity error flip-flop (TVPERF) is set to indicate existence o~ a `~ ~ertical parity error. When the LCP reconnects to the S~stem ;` 10 and terminates the "Write" operation, the Result D0scriptor ~ 25 R/D sent to the System 10 at STC 7 will indicate the parity b error.

Referring to FIG. 7C, there is seen a simplified log~c .
chart showinO the "Read" operation. A '~Read" operation is , 3 ~

.. .
... ,._. ... .

z~

-~ gen~rally accomplished in conjunction with some ~orm of "Write" operation. As an example, assuming th~t a '1Writ~"
ope~ation has been completed and the peripheral terminal unit 50 has responded with an ackno~ledge character (ACK)~
indicating that the peripheral ter~inal unit 50 i9 now capable of sending information Again, æssuming there will be no delay in receipt of data from the peripheral terminal uLnit 50, and that one buffer load of data will be received fol~owed by a partial buffer of data containing an ending code. It is also assumed that the ending code w.ill be recei~ed in such a way that it will be placed in the last.
character posi~i¢n (CD digits) of a word in the LCP buffer 2500 ~FIG- 6C)-General Flow Path: The foLlowing paragraph~ (a~ throllgh (1) - 15 describe the actions of the LCP during transfer of data from : the peripheral terminal unit 50 to the LCP, and also from the ~CP over to the System 10.
(a) Disconnect from ~ain System 10: referring to FIG.
7C, at STC 6~ when a "Read" in~truction is specified in the ` 20 Command Descriptor C/D, from the System, the READF ~read ;~ flip-flop: located on the data ~low card; the logic state of the read flip-flop i~ controlled by output levels from the OP code register; the set state of RE~D~ indicates that a nRead" operation is being performed b~ the System) i9 set.
The LCP enables setting of the LPW register 24W to logic 15~ ~ then steps to STC 1, disconnecting from the System 10 I to receive data from the peripheral te~minal unit 50. The terminal bu9 multiplexor 24X2 (FIG. 6D) select A level (SLAR~q) is active, and SLBR~u~, SLAIN and SBBIN levels are inacti~e to provide a path for data from the UART 31 over to the LCP b~ffer 250~.
(b) Receipt and Storage of Data from Terminal Unit:
referring to FIG. 7C, at STC 1, with READF ~et~ the termi~lal start (TERST) leve' is active. This TERST level causes the UART 31 to be master cleared and enables the setting of TER~CTF (terminal active flip-flop; located on terminal control card; the logic state of this flip-flop is controlled `by TERST, TREC~ and SENDF; the set state of T~MAC~F indicates - 10 that the terminal control section Gf the LCP has been acti~ated for a "~ead" or a "Write~ operation) to activate terminal control logic, ~EAD~ also enables the setting of the terminal recei~e flip-flop (TRECF) to allow recelpt of data from the peripheral terminal unit 50. The buffer 2500 has its address preset to MADR location 255 and if the even flip-flop (EVNF) i~ not already set, its setting is enabled to initiate co~trol of buffer addressing. Data characters are transferred ~erially ~rom the peripheral terminal unit 50 to the UART 31 in the LCP~ and the UART checks each character for even vertical parity.
(b-l) Receipt of First ~haracter and Generation of ~ertiGal Parity: with the terminal recei~e flip-flop ~TRECF) ;~ ~et, and the data store flip~flop (DATASTF~,in a reset ~tate, receipt o~ the first character cau~es the data ! 25 received level (DR) to be active. The DR le~el enables ~etting of the reset UA~T flip-flop (RSU~T~ and also the terminal busy flip~flop ~ ~SYF). The e~en flip-flop~ E~NF, is set, causing the buf~er address to be incremented to ~DR
location 0. The setting of the data store flip-flop, ~A~ASTF, ~ .
1 .$ : ' ~6~6~
:- -and the resettin~ of E~N~ are then enabled, in preparation for storing the first character in the bufferO With RSUARTF
s~t, the SLARAM level is generated which places the first chal~cter on the AB digits and al90 on the CD digits of the - 5 terminal bus 47~ forming a complete word. A parity bit is not included with this word. The contents of the terminal bu~ 47 are applied to the ~ertical parity generator/checker 48 of FIG. 6D. Parity for the word on the terminal bus 47 i~ ganerated a~d a flip-flop, used to designate odd vertical parit~ is set or reset, as applicable to indicate parity~
until receipt o~ a second c~aracter from the peripheral terminal unit 50.
(b-2) Storage of First Character in Buffer: with the data store flip-flop DATAST~ set, the reset state of EVNF
causes the buffer write enable A (ERWA) le~el to be active.
The System ~rite Enable (WESYS) level i~ al90 active, and ~` thes~ two levels provide the Write~Enable input for the AB
~ and CD digits of the buffer network. The first character is '~ then stored both in the AB and the CD digit locations of MADR
location 0 of Memory Address Register 36. Transfer of the first character from the UART 31 to the bu~fer 2500 causes i the resst UART flip-~lop ~RSUARTF) to be reset. The data recsive level (DR) is then made inactive, followed by the resetting of D~TASTF (Data Store Flip-Flop). Thl~
combination of logic prepares the UA~T 31 to accept the ' second character from the peripheral terminal unit 50.
I (b-33 Receipt and Storage of Second Character: when the second character is received by the UART 31, the data receive level (DR) i3 again made actiYe and RSUARTF is set3 ' ~`
- ~26 -. .

6~:

This logic in combination with the res~t state of ~he e~en ~lip-flop EVNF inhibits the buffer address from being incremented. The Setting of` the data store flip-~;lop DATAST~
and the e~en flip-flop E-v~ are then enabled in preparation ~or s~oring the second character in the buffer. The terminal bus multiplexor select A level, SLARAM, i5 still act.ive and the character is placed on both the AB and the C~ digits o~
the terminal bus 47. The contents of the term1nal bus 47 are-again ~pplied to the vertical parity generator/checker 48.
Parity is generated for the word on the terminal bus 47 and is compared with the parity generated during receipt of the firs+ characterO From the results of the comparison, a single parity bit is generated for the first and second characters.
With the data store flip-~lop DATASTF and the even flip-flop EVN~ set, the ER~B level (Write Enable level for CD
digits of LCP buffer) is generated and the second character is stored in the last character position (CD digits) of ' buffer 25 at address location MADR 0, o~erwriting the t, 20 character previously placed there. The character on the AB digits o~ the tèrminal bus 47 is not stored in the buffer ~ 2500 because the ERWA le~el is not acti~e (~RWA 1s the Write i Enable level for the AB.digits of the LCP bu~fer~. A parity bit from the vertical parity generator/checker 48 is added 25 - to the complete word now contained in the Memory Address Register at MADR 0.
(b-4) Receipt of Additional Characters and Start of Block Check Character (BCC)-Accwmulation: additional character~
are accepted by the LCY. With the receipt of each character~
', `

.

Z~2 the logic state o-f the even flip-flop EVNF i3 complemented to control incrementing of the Memory Address Register 36, so as to place data into the buffer 250G in word format.
With the receipt of the "start of h~adingJstart of text"
character (SoH/STX3 from the peripheral terminal unit 50 7 the block check character register 33 o~ FIG. 6D is enabled and each character fallowing the SOH~STX character is applied - to the BCCR 33 to accumulate a block check character B~C
for the message ~eing received. Acc~mulation of a BCC will continue through receipt of the first buffer load of data and through receipt of succeeding buffer loads of data until the ending code (ETX character) is rece~-ed. The actions that occur when an ending code i~ recelved will be described ~ubsequently hereinafter.
(c~ Buffer Filled~ ~ihen the LCP b~lffer 2504 is completely filled with data, the even flip-flop E~NF and the : Memo~y Address MADR 252 level ~re se-t, e~abling the setting of the buffer transfer flip-flop (BFXFRF). The setting of i BFXFRF indicates that the L~P buffer Z500 needs service 9 and the LCP initiates a request for a reconnection to the System 10 .
(d) Request for ~econnection to System 10: a~ter disconnection, STC 1, the LCP initiates a request ~or a re~onnection to the System by enabling the setting o~ the j 25 LCP request flip-~lop LCPRQF. The setting of the I/O send 3 flip-flop (IOSF) is enabled alqo, to condition the data 3 lines for tran fer of data to t~e System 10~ and the ~etting of the Memory Address MADR 2~3 (FIG. 6C) is enabled to allow acces~ to the Descriptor Li~ D/L. The LCP then steps -to .
!

.
~ - 12~ ~

- l -- ~

2~:

SIY~ 5 to send the Descriptor Lillk D/l, and the LPW to the System 10.
- The term M~DR refers to Memory Address le~els. These are generated on t~e TeIminal Control Card from outputs of the Memory Address Register 36. These levels represent address locations, shown in Table Y~I, in the LCP buffer 2500 - ...... ......... ~FIG.6C) which ar~ ~eserved for the following:

TABLE XI
Location Description - 10 251 ~ext-to~last data ~ord 252 Last data word 253 Descriptor link information word ~54 Descriptor link information word 25~ Descriptor link LPW
When one of the eight LCP addres~ le~els, LCPADn,is recei~ed from the as-sociated Distributio~ Card 200d during . the reconnection sequence~ then the LCP address level, LCPADL, is active. ~he LCPADL address le~el is generated on the ~erminal Control Card w~en the applicable LCPADn level is active. The LCPADn level also g~nerates the gate system level, GATSY~ to enable the LCP bac~plane network.
The ~CP connected (LCPCoN3 level i5 sent to the Distribution Card 200d to indicate that the LCP is reco~lected. The SL~IN le~el is acti~e and the SL~IN~ SLARAM, and the SLB~I
le~els are inacti~e i~ order to allow the Descriptor Link . D/L to be transferred to the Latch Register 49 (FIG. 6D~.
.
.

12g (c) Transfer of Descriptor LinX D/L ~ld the.Descriptor Lin~ LPW: in FIG~ 7C, at STC 5~ the transmit flip-flop - ~XMITF) is set. The transmit flip-flop is located on the -- ~ystem Logic card and the set state indicat~s that the LCP is transferring data to the System 10, thus, acti~ating t~e ~Readl' mod~lle of the LCP. LCP transfers the Descriptor Lin~ D/L and the lQngitudinal parity ~ord LP~ ~previously received at STC 6) back to the Syst~m 10. The LCP then enables setting of the LPW register 24 to logic nl's", and ` 10 steps to STC 4 to transfer data to the System 10.
(~) Transfer o~ Data to System 10: at STC 4 o~ FIG.
7C, the transmit f~ip-flop X~IIT~ and the I~O send flip-flop, IOSF, are stil] in the "setn state from the operation at STC 5. The asynchronous strobe flip-flop (~SYNCF) is set to enable asynchronous transfer of data to the System 10.
Data is transferred from the LCP buffer 2500 ~ by way of the data latch register 49 (FIG. 6D) to the System 10 (via the s~stem interface 22si ~ FIG. 6C). Tra~s~er is accomplished one word (plus a pari~y bit) at a time. The LCP strobe le~el ~0 LCPSTL accompanies the transfer of each word, and as each word is received by the System lO, the System sends a strobe pulse to ac~nowledge receipt of a word. Each word placed on the t~rminal bus 47 of ~IG. 6D for trans*er to the System 10 i~ applied simultaneously to the latch register 49 and the LPW register 24 . The LPW register 24 accumulates the lo~gitudinal parity word LPW during the data transfer. When the last ~ata word address of the LCP buffer 250 (MAD~ 252) is attained, the synnhronous flip-flop (S~, which is located ; on the Terminal Control Card and is set when the LCP is als~

` ' .

~. ~aj~ _ 130 --2~5~

transferring data ~.o the peripheral terminal unit) is set, resulting in the development of the synchronous level, SFL, and then the LCP steps over to STC 12 to send an LPW to the System 10.
(g) Transmission of Iongitudinal Parity Word to System 10: in FIG. 7C at STC 12, the LPW accumulated in the LPW
register 24 during operation at STC 4, is sent to the System 10. The LCP then enables setting of the LPW register 24 to logic "l's" and steps to STC 1 to receive additional data from the peripheral terminal unit 50 (via the terminal unit : device interface 22di of FIG. 6C). After this, the LCP
steps to STC 5 to send a Descriptor Link to the Main System ~0.
(h) Receipt of Additional Data and Ending Code from Peripheral Terminal Unit: Upon the second entry to STC 1, a terminal active flip-flop (TRMACTF) and a terminal receive flip-flop (TRECF) are both in a set state from the previous operation at STC 1. The terminal receive flip-flop TRECF i5 Iocated on the terminal control card and this flip-flop is set when the LCP is receiving data from the peripheral :.
termlnal unit; the termiDal active flip-flop, T~ACTF, is ~ also located on:the terminal control card and, in its set ,~ ~
. state, indicates that the terminal control section of the LCP
~ ` ~
has been activated for~a "Read"~or "Write" operatlon. The LCP buffer address is again set to MADR 255 in~:preparation for receipt of data from the peripheral terminal unit 50.
At STC 1, the actions of the LCP while receiving the second buffer load of data fr~: the peripheral terminal unit 50 ' ~.

~ 2~ 't~

are the same as those performe~ during ths receipt of the first buffer load, up to the po.int that an ending code is received on the ter~inal ~us 47.
Assuming that pr-or to rsceipt of the end code, at S~C
-I 5 19 that the follo~ing two conditio~s exist: (1) EVNF is re~et, indicating that the next ch~racter to be recei~ed will be placed in the last character position (CD digits~
of a word; and (2) ~oth RSUARTF (Reset UART Flip~-Flop) and the data store flip-flop (DATASTF) are reset. When the ending code character is received, RSUARTF is set, pro~iding the ~ecessary logic le~el to generate the Write Enable (ERW 18) le~el for the ~nding code ~. Receipt of an ending code is recognized by the LCP when the character i3 on the terminal bus 47. Recognition of the ending code cause~ the end code le~el~ EDCODE/ to be generated, which develops the data input level (RUuM 18 IJ) for the ending code ~ RAM; the end-flag bit (ENDFG) i5 then stored in the prese~lt .~ buffer address of the buffer 25 . The setting of EY~ and oo j DATASTF is then enabled, which conditions the LCP to ~tvre the ending code in the buffer 2500. With EVNF set, the ER~B
(Write Enable level for CD digits) le~el is acti~e and the character is stored in the last character position o~ the j same word address in ~hich the end-fla~ level, ENDFG, is stored.
i 25 (i) Check of BCC and ~e~uest for Reconnection to j System 10: with DATASTF set, the EDCOD~ le~el enables the . ~etting of the end flip-flop (BNDF)O The LCP now recei~es a block check character (BCC) from the peripheral t~rminal unit 50 and checks it against the accumulated BCC in the .

- 13~ _ block check character register 330 The setting of the end *lip-flop E~DF causes the termi~lal receive ~lip-*lop TR~C~
~o be rese~ and the te ~inal compiete level (TMCMP) to be acti~e, termin~ting the actions of -~ne teI~inal ^ontrol section of the LCP~ The LCP then initiates a request for a reconnection to the System and steps from STC 1 to STC 5 to send the Descriptor Link D/L to the System 10.
(~) Trans*er of Descriptor Li.nk D/L and the Descriptor Link LPW: ~s in the prec0ding reconnection to the System, at STC ~ the LCP sends the Descriptor Link D/L and the LPW
to the System, an.d then steps to STC 11 (Read) to transfer data t~ the System 10.
. (k) Transfer of Data to System 10: at STC 4~ the actions of the LCP are the same as described before at STC 4~ until the word containing the ending cocle character is placed on the transfer bus for transfer to the System 10. ~ecognition o~ the ending code causes the System end le~el (SYSEND) to .'; be developed9 and the LCP steps to STC 1~ to send an LPW to - the System 10.
(1) Transmission of LPW and Result Descriptor R/D to ' ` System 10: the LCP sends the ~PW accumulated in the LPW
t register 24W to the System lOn A~ter the LPW is sent, ~ince `; the terminate complete level (~MCMP~ is now acti~e, indicating I that there is no more data to be transferred, the LCP steps to STC 7 to send a Result Descriptor R/D to the System 10.
.. ` At STC 7, the LCP sends a Result Descriptor R/D to the System 10, then steps to STC 15.~FIG. 7D), ~nd sends an ~PW7 then returns to idle at STC 3 to await anoth~r instruction from the System lOo ---- --The above discussion has involved the general flow path for a "Read" opera~ion in which more than one buffer load of data was transferred from a peripheral to the Main System, and in which the operation was concluded by receipt of an ending code.
However, during a "Read" operation, other situations may occ~lr to cause alternate logic flow paths and the handliny of possible error conditions. The following sec-tions (a) through (d) indicate the actions of the LCP when modifications to the original "Readl' instructions are made either by the System l0 or by the LCP:
(a) Receipt of Time-Out Level: referring now to FIG.7E, which is made of two sheets, 7E-l and 7E-2; at STC
; 1, with operation of the one-second timer not inhibited7 and data being received by the LCP from the peripheral terminal unit 50; if the sending of data is interrupted !
for a period of one second, the time-out level (TIMOUTL) is generated. With TIMOUTL active, the end flip-flop (ENDF) is set, and the terminal complete level (TMCMP) is gener~-ted. A request for reconnection to the System l0 is initia-ted and the LCP steps over to STC 5. At STC 5, with the end flip-flop (ENDF) set, the Read operation is terminated and the LCP steps over to STC 7 to send a Result Descriptor ; R/D to the System l0. A time-out level can also be receiv-ed with the LCP at STC 3 as can be seen in FIG. 7E at STC
3 "idle status".
(b) Transmission Still Expected from Peripheral TermLnal Unit: in FIG. 7E, at STC l, with the LCP condi-tioned to receive data from the peripheral terminal unit 50, ~hen if ..
~ - 134 -'~ ' .

data is not bein~ _eceived, the ~CP steps immediately to STC 3 in order to be in a condition to receive a conditional Ca_lCel ~ns ~Iction from the System 10~ The LCP will retur from Sl~ 3 over to STC 1 if a data transmis~icn begins.
(c) Re~uest for Emergency Reco7,lnection: during trans~er o~ data from the peripheral terminal unit 50 to the LCP, when the buffer 2500 is completely filled, a buffer transfer flip-flop (BFX~RF) is set9 initiating a re~uest for - a reconnection to the System 10 to 3tore data. (The buffer transfer flip-~lop (~FXFRF) ~is se~ when the LCP bu~fer 2500 is filled wlth data 4rom the peripheral tsrminal unit 50, or when emptied durin~ transfer of data from the LCP to the peripheral terminal unit). I~ a reconnection is not completed prior to the time the UART 31 receives another character, the emergency request le~el (EMRREQ) is generated.
The E.~RREQ level is ~ent to the associated Distribution Card 200d to initiate an emergency reque t for a reconnection to ~ the System 10.
i (d) ~eceipt of Ending Code (AB digits): ghe action~
~0 of the LCP relating to receipt of an ending code, which will ~¦ be placed on the AB digits (~irst character~ of a word, are more varied than those involved with receipt of an ending code to be placed on the CD digits of a word. This condition e~ists becau e a tra~smission ~rom the peripheral te~minal unit may consist of data followed by an ending code, or it '¦ m~ con~ist merely of an ending code by itself. Additionally, decrementing of the System Memo~ Address may or may not be required when qtoring the ending code, in order to reflect the accurate location of the ending code in System ~emory 10 .
"i ,, .; .

, - 13~ -!
6~2 -T~LUS~ the follo~ing actiorLs of the LCP for these Y~riouS
~- conditions are discussed below in paragraph~ dl and d2:
(d~) Receipt o~ Ending Code Following Dat~- if the ending code follows a ser~es of data characters ana is received on the terminal bus 47 when the e~en flip-flop (EVNF) is set, ~ the character, when stored, will be placed in the AB digit position of a word in the LCP buffer 2500. When the - character is received, the end code l~vel (EDCODE) is ger.erated, causing RAL~t 18 L ~Write end-flag le~el) to be acti~e, and the end-flag level (ENDFG) is stored in the presentl~J current bu~fer address. (The end oode le~el (EDCODE) i5 gsnerated on the ter~inal cont~ol card ~hen ~1 end code character i~ in the A and B digits of the terminal bus 47.
The end-flag le~el, E~D~G, is generat~d on the data flow -- 15 card from Rl~hl 18 L, and ~hen acti~e, this le~el identifies the address of an end code in the LCP buffer ~500. ~te write end-flag le~el (~UhM 18 L) is the dat~ input le~el for the ; end-flag ~M of the LCP buf~er 25~o3. The set state of the e~en ~lip-flop (EVNF) then ca~tses the buffer address to be !' 20 incremented to the next word address- The setting of the dat~ store flip-flop (D~TASTF) and the complementing of t~e even flip-~lop (EVMFj are then enabled. ~ith EV~ reset, the ~rite enable A (ERWA) level is ~enerated and the ending code - is stored in the AB digits of the buffer address ~ollo~ing the one in which the end-flag leYel (EL~DFG) was stored.
The LCP tnen initiates ~ request for reconnection to the ~ System to trans~er data and the eIlding code to the Main ` System 10. - -During transfe~ of final data from the LCP bu~er 2500 to the System 10 at STC 4, a~s ending code in the AB digits .. . .

of a word will ~Je recognized ~7hen END~G (end-flag le~el) level is act;ive and the system end c~de level (SYSEND) is inacti~e. This logic combination indicates that the next word to ~e transferred contains an end.ing code in the AB digits~ In FIG. 7E, the LCP s:teps to STC 14 to accomplish tran~fer of a single character. At STC 14 the setting of a word transfer control flip-flop (WTCF3 is enabled unconditionally. The setting of the cha~acter transfer f`lip-~lop ~CTSF) is ena'oled to specify that the character tr~nsfer sta*e was entered. The ending code is stored in System Memcry lOm, and the LCP steps first to STC 12 to send a longitudinal parity word LPW to the System 10, then steps : over to STC 7 to send a Result Descriptor R/D to the System 10 (d2) Receipt of Ending Code Only: as per ~IG. 7E, at STC 1, if the transmission from the peripheral terminal unit 50 consists of a single character (end code), it will be ~eceived on the terminal bus 47 with the e~-en flip-flop .
. E~NF in a set state, and will be placed on -the AB digit j position of a word in the ~CP buffer 2500. The character ! 20 is stored and the LCP initiates a request for recor~ecti.on to the System to transfer the character, as seen in the 3rd ~ block of FIG. 7E at STC 5. This steps over to STC 4, and i~' with the end code level (EDCODE) active, the setting of the I character end flip-flop (CHARENF) is enabled. The character is transferred (STC 14) to the System 10 and the LCP steps over to STC 12 to send a longitudinal parity word (LPW) to the System 10. At S~C 129 the set.state of CHAREN~ t-the character end flip-flop) causes the LCP to step directly to STC 9 to i~.itiate decrementing of the System Memory Address lOm.

. . .

J
' .:7 ~, - 137 _ _ . _ , . _ ......

T~en the LCP steps to STC 7 ln order to send a ~es~lt Descriptor R/D to the Syste~ 10.
(e) Receipt of Terminate Signal from System: a - termi~ate si~lal (TER~ leYel) is sent from the System to the LCP during a Read operation whenever available system memory ` ~pace designated for the LCP operation is to be exceeded~
During a Read operation9 the TE~i level may be recei~ed (~IG. 7E) at STC 4, STC 14, or STC 12. The action~ a~ the LCP ~pon receipt of the TE~M level depend upon the status - 10 count in which the LCP is operating when the TE~t le~el is reeeived, alld upon whether or not tke receipt of the TE~I
level is preceded ~y the receipt of an ending co~e character ~rom the peripheral terminal unit 50. Under these conditions, ~ the actions of the LCP are ~iscussed in the following `' 15 paragraphs el and e2:
~el~ Receipt of Terminate Signal Before End~ng Code is Recei~ed: if the LCP receives the TE~ (term~nate signal) level from the System before it has su~ficient time to receiva and store an ending code, the LCP then aots as ~ollo.ws:
el (a) The receipt of the qE~I le~el ~-hile ~he LCP is ~ransferring data to the System at STC ~, causes the terminate - flip-~lop (TE~MF) to be set, and the LCP steps over to ~T~ 12.
; A lo~gitudinal parity word LP~ is sent to the Syst~m I0 and the set state of the termina*e level (TER~) causes the LCP
` ?5 to terminate the Read operation and step over to ~T~ 7 to send a Result Descriptor R/D to the System lOo el (b) In FIG. 7E, the LCP steps from STC 4 ov~r to STC 12 after transferring a word containing an en~ing code in ~, the CD digits o~er to the Ayste~ 10~ If the TERM le~el is now r~ s~
.fL6i~

recei~red at STC lZ, the settln~ of ~e -word transfer control flip-flo~ (WTCF) is enabled, and the LCP ,e~ains n STC 12 for an additional strobe t~me. If during the ~econd strobe ti~e~ the TERM level is still active, this indicates that the ending code was not transferred. ~h~ se~ting of TE~MF
(terminate ~lip-flop) is ena~led and the LCP steps over to STC 7 to send a Result Descriptor R/~ to the System lO.
el (c~ The LCP steps from STC 4 over to STC 12 when the last word in the buffer 2500 has been trans~erred. If the TER~ le~el is now received at src 12, the LCP remains in STC 12 for additional strobe time. The word transfer control f~ip-flop (WTCF) is set and reO~ardless of the lo~ic state of the TE~M level during the second strobe time, the LCP termin~tes the Read operation and steps over to STC 7 J~ to ~end a Result Descriptor ~/~ to the System lO-el (d) The LCP will be in ST~ 14 if the last data ` word tran~ferred at STC 4 is to be followed by an en~ing c~de in the AB digits of the next word. If the terminate (TERM) level is now recei~ed at STC 149 the ending code is ~ .
not stored and the LCP steps to 5TC 12, it sends an LPW to the System, and then steps to STC 7 to send a Result , ~, Descriptor R/D to the System lO.
(e2) Receipt of Terminate Signal After Ending Code i~ Recei~ed: if the LCP receive9 thb termin~te level (TEF~I) ~ .
~rom the System lO after a~ ending code ha~ been received from the peripheral terminal unit 50, then the LCP acts as ~hown in the following paragraphs e2 (a~, e2 ~b), e2 ¦c):
e2 (a) In FIG. 7E, the LCP steps ~rom STC 4 over to STC 12 after trans~erring a word containing an ending code .

:, :,~

..... _ . _ ., _, .

,S~a~

in the CD digits to the System 10. If the TERM le~el is now recei~ed at STC 12, the se*-ting of the word transfer control flip-flop (WT~,~) is enabled and the LCP remains in STC 12 for ~ additional strobe time. X~ during the seeond strobe time, the TE~ level is no longer acti~a, this indicates that the ending code was transferred. The LCP
the~ steps over to STC 7 to send the Result Descriptor R/D
to the System 10.
-~2 (b) l~le LCP steps from STC 4 oYer to STC 14 if the last word transferred at STC 4 is to be followed by an ending code in the AB digits of a word. If the LCP
progresses through STC 1~ without recei~ing the TERM level, the ending code is tran~erred to the System 10, and the LCP steps o~er to STC 12 to ssnd a longitudinal parity word LPN. If the TEF~I level is now received at the STC 12, the LCP takes no action upon its receipt, but steps to STC 7 to send a Result Descriptor R~D to the System 10.
e2 (c) If a transmission ~rom the peripheral te~minal ' unit 50 co~sists of a single character (ending code~, then at STC 4, the LCP enables the setting of the charaoter end flip-flop (CHARENF) and steps o~er to STC 12 to send a longitudinal parity word LPW. At STC 12, if the TE~M le~el i~ now received, the LCP will remain in STC 12 for an additional strobe time. If during the second strobe time, ' 25 the TERM level is stil~ active, this indicates that only -~ the first half of the word containing the ending code was transferred and the System Memory A~dress was not incre~ented to the next word address. The ~GP steps over to ~IC 7 to send a Result Descriptor R/D to the System 1~. If the TER~

~

. .

~ level is inactive during the second ~trobe time, this -- indicates that the System Memory Address Wa9 incremented . to the next ~ord address and requires decrementi.ng. The ~et state of the character end flip-flop (CHAREN~) and the inactive state of the terminate le.-~el (~ERM) cause the LCP
~' to step over to STC g to initiate decrementing o~ the System `~ Memory Address. From STC 9, the LCP steps o~er to STC 7 to send a Result Descriptor R/D to the System 10.
.-; Error Conditions: During the course of a "Read".operation7 certain error conditions may occur which will be acte~ upon by the LCP, as follows:
(a) Access Error: after transmitting the emergency request (EMRREQ) le~el, if the LCP has not recei~ed a . ,~ .
recom~ection to the System 10 prior to receiYing a second character in the UART 31, the UART 31 generates a level called o~errun error level (OE). The OE le~el causes the enabling ', o~ the access error flip-flop (ACCERF~ and of the end flip-flop (E~DF). The LCP then initiates a request ~or ~ reconnection to the System 10 to terminate the Read operation i 20 and to send an error Result Descriptor R/D to the Syste~ 10.
(b) Terminal Vertical Parity Error: during tran~fer of 1 data from the UART 31 to the LCP buffer 25 , i~ the parity .~ error level (PF) is generated ~y the UART ~17 the tel~inal .~ vertical pari~.y error flip-flop (TVPERF~ is set to indicate e~istence of a vertical parity error. Ihis flip-~lop,TVPERF, ha~ a logic state which ls controlled by an output from the j LCP vertical p.arity generator/checker 48, or from the parity s error output of the UART 31 (FIG. 6D). The set state of th~
flip-flop indicates that a ~ertical parity error occurred - -'~'` i' ? ~ ) during transfer ~-r data between the LCP and ~he peripheral terminal unit 50. This flip-flop is located on a Terminal Control Card.
(c) Block Check Character Error: during the transfer of data (FIG. 6D) from the UART 31 to the LCP buffer 25 , if ' the bloc~ check character OK level (BCCOK) is not acti~e after the block check character has been chec~ed, the block ` check character error ~lip-*lop (BCCERF) is set to indicate : the existence of a block check character error. The BCCOK
level is pro~ided by decoder 34 of the block c'heck'`'cha~cter register 33 in ~IG. 6D.
Write Flip-Read Operation:
; This operation is essentially a Write operation fo$10wed by a Read operation. Basically the pre~ious discussion regarding the "Write'l operation and the '1Read" operation of ~IGS. 7B and 7C are applicable here. 1~te receipt of a Command Descriptor C/D for the "write flip read" operation into the OP code and the variant registers 42 and 43 (FIG. 6D) - respectively, causes a "Write" operation to be initiated and'a FLIP le~el (Flip Level) to be generated. Data is trans~erred from the System 10 to the periphe~al terminal unit 50 during the "Write" portion of the operation. When an ending code is recogni~ed on the terminal bus 47 during data transfer from the ~CP to the peripheral terminal unit 50 at STC l~FIG.7 2~ then the end code level (EDCODE) is generated. The EDCODE
level enables the setting of the end flip-flop (ENDF) 'indicating that'the data transfer is complete. The set state Of the end fli~-flop (ENDF? and the generatlon of the F~IP
le~e~ ena~le the setting of the raad flip-flop ~READF), 3~ 6.~

, . . .
;~ the terminal receive flip-flop (T~EC~), and t~e e~en flip-flop (EVNF), the rese~ting of the ~Tite flip-flop (l~ITF), t~e terminal busy flip-flop (~RMBSYF), and the presetting of ~he bu~fer address to ~I~DR 255. With these actions, the LCP
is conditioned to receive data from the periph~ral terminal unit 50, without reconnecting to the System 10 to receive additional instructions.
To initiate the "Read" portion of the write-Flip-Read operation, the LCP does not reconnect to the System ~0. As per FIG. 7E, from STC 1, tne LCP steps over to STC 3 to await a transmission from the peripheral terminal unit 50.
- Receipt of the first character from ths peripheral terminal unit 50 causes the DR level (Data Received3 in the UART 31 to be active, enabling the setting of the reset UART flip-flop (RSUARTF) and the terminal busy flip-flop (IF~SYF).
The setting of the terminal busy flip-flop ca~sss the LCP to return to S~C 1 to receive the data. The "Read'l operation progresses through to completion, subject to the same conditions discussed previously for a re~lar Read operation.
Test Operation: The ~test operation~ pro~ides the System 10 ~ith the capability ~or determining the operational statu~ of the LCP without requiring a trans~er of data to or from ~he ~ .System Me~ory lOm. Located on a data flow card is a test - flip-flop (TESTF). Ihe logic state of this flip-flop is controlled by output levels from the OP cod~ register 42, FIG. 6D. The set sta~e indicates that a test instruotion was received from the 5ystem 10. ~n ~IG~ 7E, at STC 11, wi~h the test ~lip-flop (TESTF) set, the LCP has no ~equirement to step to STC 6 to receiqe a Descriptor Link D/L. It steps .
, ~ 3 -.

~ 3~

. .
- instead to STC 7 to return a Resul~ ~esc-~iptor ~/D to t~.e System 10. From STC 7, the LCP s-teps o~er to STC 15, and then STC 3 (idle), where it remains until another Com~.and - Descriptor C/D i9 receiv~d. Under normal conditiosls, tne Result Descriptor R/D sent to the Syste~ 10 for a "test operat~on" ~ill have all bits equal to zero. The System 10 will recognize, by this condition, that the LCP is oper~tional~
Test Enable Operation: The receipt o~ a Command Descriptor C/D containing a n test anable" inst~uction conditions the DCP
so that the peripheral terminal unit 50 ~an initia~e a communication with the Sy~tem 10. The peripharal te~inal . unit 50 initiates a req~est ~or cQ~munication b~ sending an inquiry character (ENQ) to the LCP. Upon receipt of the inquiry character ~ENQ), the "test enable" operation is terminated and the Syste~ initiates a "Read" operation to receive data from the peripheral terminal unit 50. If the `! terminal unit sends any other character but an ENQ inqulry character9 the character will not be recognized and the LCP
~ will take no action. The "test en~blel' operation operates i 20 ~in reference to FIG. 7E) as follows:
At STC 3, upon receipt of ~ "test enable" in~truction, ~ the variant register flip-flop No. 3 ~AR3F~ i~ set. The ~ 4) F" represents the 4 ~ariant register le~els.
The3e are generated on the Data Flow Card by outputs o~ the i, 25 variant register 43, FIG. 6D. The logic r~tate of these levels s i dependent upon the numerical value contained in the variant digit 1 of the Comma~d Descriptor CjD. The setting of VAR3~
i~ inhibits the setting of the test flip-flop (TESTF) but allows the read flip-flop (READF) to be se-t. The LCP steps o~er to 3. ~

. , i , ~ 144 -~ ~ ~L6~
:; . .
!
S~ 11 to receive the Command Descriptor longitudinal parit.y wor~ LPW from the System lO~ and then steps over to STC 6 to receive the Descriptor Link D/L from the System. At S~C 6, . b~cause the "nead" flip-~lop (~ADF) is set, the LCP
disconnects from the Syste~ 10 and steps over to STC 1 to receive an inquirr character (ENQ) from the peripheral terminal unit 50. At STC l,(unless an i~lquiry character (ENQ).is received immediately) the LCP steps over to STC 3 to await a tr~nsmission from the peripheral terminal unit 50.
When the termina} unit transmits, the terminal busy flip-~lop . ~TRMBSYF) is set, causing the LCP to step over to STC 1 to receive the inquiry character (E~Q). When the ENQ is recei~ed, the set state of the ~ariànt register level, YAR3F7 inhibits the LCP from stepping over to STC 4 and also .. 15 ~ihibiting the t~nsfer of the character to the System lO.
Instead the ~CP s.teps over to STC 7 to retul~ a Result - ~escriptor R/D to signify to t~e System 10 t.hat the."test enable" operation is complete.
Conditional Cancel Operation: The "conditional cancel opera*ion" provides the System 10 with a capability to cancel preYiously sent Command Descriptor C/D containing a "Read'i operation. Referring to FIG. 7E, if the LCP has initiated a "Read" or a "Write flip ~ea~" operation, but the expected data transfer from the peripheral te~ninal unit 50 is not in progress, the LCP will remain at STC 3 awaiting a possible ~conditional cancel" instruction. I~ a conditional cancel instruction is now received, the ~Read" operation is cance;led and the cancel flip ~lop (C~NCF) is set. This cancellatlon will not be effect~ated unless the LCY is at .. 145 ~
.~! a. . G~

~D~

STC 3~ The LCP then steps over to STC 11 to receive a Command Descriptor longitudi~al pa~ity word LPW from the Syste~ 10. ~he set state of the c~neel flip-flop C~NCF
inhibits the L5P from stepping to STC 6. Inst~ad, the LCP
steps over to STC 7 'o return a Result Descriptor R/D to the Sy~tem 10, indicating that the conditional cancel operation i5 completed.
Echo Operation: The "echo OperatiQn~ is a maintenance aid to trouble shooting of the LCP. This operation begins with a ~Write" operation in which data is transferred from System Memory 10m o~er to the LCP buffer 2500. ~his is followed by a "Read" operation in which the same data is tranctferred back to System Memory 10 . Assuming9 for example, that less than a full buf~er load of data ~ill be trans~erred and that the operation will be termina~ed by receipt of an ~- ending code in the last character position of a word; and ~ince the "echo operation~ is essent.ially a Write opera~ion ~ollowed by a Read operation, the following dlscussion will in~olve only t~ose LCP actions which ars unique to the echo ~i 20 operation. (Read and the Write operations were previously discussed in connection with FIGS. 7B and 7C). No~ referring 1 to FIG 7E~ at STC 6~ and with the echo flip-flop (ECHOF~ set, the LCP steps over to STC 8 to accept data from the S~stem 10.
~' Beginning at STC 8, the LCP operates as. previously discussed `'` 25 during a regular "Write~' operation up to the point that the : LCP receives an ending code and then steps over to STC 12.
At STC 12, althvugh no data i~ ~o be t~ansferred from the LCP
~; to the peri~heral terminal unit 50, the LCP disconnects ~rom th~ Syste~ 10 by stepping momentarily over to STC 1. Nhen -' .

~1~6 ~
~, .

:

.
disconnected at STC 1, the LCP initiates a request for reconnection to the System 10 by enabling the setting of:
the LCP request flip-flop (LCPRQF); the I/O send flip-flop (IOSF); and by the presetting of the buffer address to MADR
253 (Descriptor Link, FIG.6C). me LCP then steps over to STC 5 to send the Descriptor Link D/L to the System 10.
At STC 5, the LCP transfers the Descriptor ~ink D/L to the System 10. The set state of the echo flip-flop (ECHOF) then causes the LCP to step over to STC 4 to return data ?
in the bufer 2500 back to the System Memory 10m. Beginning - at STC 4~ data is transferred from the LCP over to the System 10. The actions performed by the LCP are as those previously described during a regular "Read" operation up to the point that the LCP identifies an ending code on the . terminal bus 47 and then steps over to STC 12. At STC 12, i the Read operation is completed and the set state of the ¦ echo flip-flop (ECHOF) causes the LCP to step over to STC 7 to return a Result Descriptor R/D over to the System 10. Return of Result Descriptor R/~: ~IG. 7D is a simplifi-~ 20 ed logic flow diagram regarding the return of the Result ; Descriptor R/D. The LCP steps over to STC 7 to return a i Result Descriptor R/D to the System 10 under any of the ~llowing conditions listed as a, b, c, d ' a~ At STC 12 or STC 9 when a "Read" or an echo ; ~ . operation is completed.
bo At STC 5 when a "Write" operation is completed.
c. At STC 11 when any one of the following conditions occur:
(cl~ A descriptor error occurred;

7 -I ;~, ~
. ".:~.

~c2) A test operat.ioI~ i5 specified hy the Co~mand -. Descriptor C/D being e~ecuted;
(c3) The conditional cance~ flip-~lop (CANCF) i~ set.
d. At STC 6 if a vertical or a longitudinal p~rity error has occurred.
At STC 7, if the transmit flip-flop ~IITF) is not set,.
. it is set at this time to acti~ate the LCP Read module. The terminal bus multiplexor select A level (SL~R~I) and the terminal bus multiple-;or select B level (SLBRA~I) are both acti~e, which allows the terminal bus multiplexor networ~
~24X2 of FIG. 6D) to select a word ~ade up of Result : Descriptor levels for transmission to the System 10. Whe~
the ~esult Descriptor word is placed in ths data latches 7 49, it i~ also applied to the LPW register 24 to ge~erate a~ I;PW
for the Result ~escriptor transfer. The LCP then steps over to STC 15 to send *he R/D LPW to the System 10~
At STC 15, the terminal bus multiplexor select ~ level (SLARU~ .inacti~e and the terminal bus multiple~or select B le~el (SLBRUL~I) is active, which al~ows the terminal hus multiplexor networ~ (~4 2 of FIG. 6D) to select outputs o.
t~e LP~ register 24W for transmission to the System lOo .
(The SL~ M is used in conjunction wi-th the SL~R~I tQ select one of four illpUts to the termin~l bus multiplexor n~wark).
These are generate~ on the System Logic Card from outpnts o~
: 25 . the SqC decoder 54 of FIG. 6~. The LCP transfers the ~PW, resets selected logic levels to a begiI~ing sta*e, and then steps over to STC 3. . The LCP re~ains at STC 3 until another Command Descriptor C/D is =eceived.

: .

r~ f ~ 8 -f , ' , I~ s~mm~ry the T.CP operates in two "modes" ~-. the "off-line" mode and the "on-line" mode~
Off-line mode:
Qperation of the LCP/Terminal Unit combination in an off-line mode is for the purpose of performing maintenance f~ctions. In the field, a variet~ of operations can ba performed to ~erify the condition of the LCP or for simple trouble shooting. Thes~ operations can be carried out without effecting the normal operation of other LCP's in the same Base Uodule.
On-line mode:
- The two basic operations controlled by the LCP in the on-line mode operations are (1) a Write operation in which data is received from the System by the LCP and . which data is transferred to the peripheral terminal unit~
and ~2? a Read operation in which data is received from the terminal unit by L~P and i9 transferred to the System Memory m - In addition to these basic operations, ~he LCP can change from a "Write~ to a "Read" operation with a ~ingle inStrUCtiOll, and can also perform selected test operations~
The fol~owing items represent the specific operations which the ~CP can perform by means of program instructions from the Main ~ystem 10. This is done by means of Command Descriptors (C/D) and herein follows a brief summaI~ o~
what is accomplished by each operation.
` Table XII here below su~m~rizes the specific operatlons which the LCP can perform: :

.
.

'~ - 11~9-TABLE XII
a. Write d. Test b. Rea~ e. Tesit ~nab~e c. Write Flip Read f. Conditional Cancel . g. Echo Command Descriptors.
Ihe Command Descriptors (C/D) are instructions ~rom the Main System 10 to the LCP regarding certain operations to be performed. The following items wîll s~ummarize briefly the Command Descriptors associated with each of the instructions (o~ Table XII) from the Main Sy~tem 10:
~a) Write:
The ~Write" Command Descriptor is an instruction to t~anafer data from System Me~ory lOm to the peripheral terminal unit desired 9 for example, such a~ peripheral terminal i~ . unit 50. The LCP accepts data from the System 10 until the . LCP buffer ~500, ~or example, is full, or until the ~ata tsalts~er is stopped by t~e receipt of an "ending oode" or a `j "terminate" signal from the Main System 10. When the LCP
buffer 25 is ~ull, or when an:"ending code" i5 received, the LCP transfers the contents of ~he ~u~er Z500 to the ~` peripheral *erminal unit 50. The "Write" Command Descriptor ! ii~i identified a~ howm in Table XIII belowt XIII : (Writ~ C/D) ~ 25 ~ 3L~_nes~ U.~i `' Ag 0.
A4 ~ 1 OP ~Digit A:L O

B2 O ~ Variant Digit 1 ~ O .

.

, , ~ , , . , ~ ... ~ .......................................... .
.

`
~3.~

~b) Read:
The ~Read" Command Descriptor is an instruction to trans~er data from the peripheral terminal unit in~ol~ed, such as u~it 50, over to the System Memory lOm. 'l~e LCP
~irst accepts data ~rom the peripheral terminal unit 50 until the LCP buffer 25 i~ ~ull, or until the data transfer is stopped by the receipt af an "ending code" ~rom the peripheral termina~ unit. When the LCP buf~er 25 is full, (or when the ending co~e is receivsd), the LCP
transfers the contents of the buffer 2500 o~er to the System Memory lOm9 unless the Main System 10 sends a "terminate" signal to 9~0p the Read operation ~ecau~Q Syst~m Memory space is not a~ailable to store.any more data. If, after initiating a Read operation, the LCP receiYe~ no data for a period o~ on~ second, the LCP "times out" and sends Result Descriptor (R/D) to the Main System lO. The one-seco~d timing in~erval can be inhlbited by setting a bit 1) of the variant digit 1 of the Co~mand Descriptor e~ual j to 1. Table XIV below ~hows the "Read" C/D.
TABLE XIV : (Read C/D) Data_~ines Di~it ~alue A~ 1 ?
;l A4 `~ OP Di~it ~,~ Z5 . hl 0 ; - B8 0 B2 Dee ~ariant Digit ;1 3 note ~ Bl i equal to l, the one-second time-out pariod, ;i~ allow~d to the t rminal u~it to respond, is inhibited.

~ , Q ' `

b - 15`1 -(c) Write flip Read~ -The "Write flip Read" Command Descriptor is an instruction to the LCP to accomplish a Write operation, at the conclu~ion of whicn an immedia~e Read operati.o~ is performed witho-~t any intervention ~rom the Main Sys.tem 10~ Data is accepted ~rom the Main Sy~tem 10 and transferred to the peripheral termina; unit until an "ending code" i~ receiYed. Upon receipt of the ending code from the Main System 10 7 the LCP
: transfers the ending code to the peripheral terminal unit and then changes to the Read Mode. The LCP then accepts data from the peripheral terminal unit and transfers it to t~e System Memory 10m ul~til an ending code i~ received from the peripheral terminal units~ or until a terminate signal is received from the Main System 10. ~f, after beginnin8 of the Read portion of the operation, the LCP receive~ no data . for a period o~ one-second, then the LCP ~times-out" a~ld . send~ a Result Descriptor (R/D~ to the Main System 10~ 0 c~urse, the one-second time inter~al can be inhibi~ed if desired, b~ setting the bit Bl of the ~ariant digit 1 of ~ 20 the Command Descriptor equal to one. Table XV below ,~ illustrate~ the ~Write flip Read" Command Desoriptor.
: (Write flip Read U/D) ~8 ~ ) ~ 25 A2 1 3 OP Digit :. Al 0 ~
... .
B8 . 1 ~
~; ~4 0 .
~i 3 B2 o Variant Digit Bl see n~te ~ If Bl is equal to 1, the one-second time~out period, `¦ allowed to the ter~inal ~nit to respond, i~ inhibi~edO
J
', ~ v 152 _ - .

:`
(d) Test The "test" Command De~criptor is an in~truction to the LSP to indlcate its "operational status" by re-turning a-Result Descriptor (R/D) to the Main System 10. If the LCP
is present and available, the Result Descriptor will be e~ual to all "O~s~. Table XVI below shows the Test CommaAa De~criptor:
T~BLE XVI : (Test C/D) -~at~a LinesDi it Value A8 ~
Aæ 1 OP Digit ~ Al 0 : B8 0 ~:
B4 0 Variant Digit 1 Bl 0 (e) Test Enable:
The "test enable~ Command Descriptor is an instruction to the LCP to monitor incoming data from the peripheral terminal unit~ and upon receipt of an Inquiry Character (ENQ), to form and transmit a Result Descriptor (R/D) to the System 10. ~his instruotion i9 used to allow the peripheral terminal unit to initiate a communication with the Main System 10. Table X~II below illustrates this Command .
, .

z~

TABI,E XVII : (Test Enable C/~) Data Lines B3~L~

J OP Digit Al O 3 ~8 O

B2 ~ ~ariant Digit Bl see J
` note If Bl is equal to 1, the one second time-out period, ~ allowed to the termi~al unit to respond, is inhibited.
(f~ Conditional Cancel:
~he "Condit~onal Cancel" Command Descriptor is an instruction to the LCP to initiate cancellation of another Command Descriptor under certain conditions. When the Conditional Cancel Command Descriptor i3 received by the - LCP, and, if data is not being received from the peripheral terminal unit during the applicable portion of a Read oper~tion, then the previous Command Descriptor will be cancelled. This C/D is shown in Table X~
(Conditional Cancel C/D) ~ Data Lines `~ 25 A~ O
'~ A4 ~ OP Dlgit `' Al O J

~ 3O B4 O Variant Digit 1 -`i Bl ' :, . , .

~ .
. . ~

~g) Echo:
Ib.e "~cho" Command Descriptor is an instruction to the LCP to accept a full buffer of data (or less~ from the ~lain System 10 and ~hen to return the sa~le data back to the Ma.in System 10 to be stored. This provides a maintenance check and trouble shooting dia~osis cycle for the System-LCP
operations. Table XIX illustrates this Echo Command Descriptor.
- T~BLF XIX : (Echo C/D~
- 10 , Data Line Digit Value A4 ~ OP Digit Al 1 B8 O ~ . .
B4 ~ Variant Digit 1 ~1 0 ' Having described a digital data processing system ~ 20 ln~ol~in~ a plurality of I/O Subsystems for managing data '~ tran~fer operations and including certain modular units~
such.as the Line Control Processor, the Base Module, the Input-Output Tr~nslator and the interrelation~hips thereof, the following claims are ~ade:
'i ' ' " ' .~ , ~, ~1 ., .

. . ~

'i - 155 -~ ., .

Claims (11)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:-

1. In a digital system for the transfer and control of digital information between a first main system which includes a processor with main memory having an I/O translator interface unit, and a plurality of remote peripheral terminal units, wherein each peripheral terminal unit is connected to the main system via a corresponding line control processor, and wherein groups of said line control processors at a given site are organized into Base Modules, a Base Module unit comprising-(a) a plurality of line control processors, each of which has its own dedicated connection to a corres-ponding peripheral terminal unit and wherein each of said line control processors is adapted to handle the particular discipline required by its corres-ponding peripheral terminal unit, each of said line control processors including a data buffer memory having sufficient memory space for storing at least one complete message block of information data and control data;
(b) a single backplane common to each of said plurality of line control processors within said Base Module, said backplane including transmission lines from each line control processor to a distribution-control means, said transmission lines being selectively activated by said distribution-control means;
(c) connection means for connecting of each said plurality of line control processors with a dedicated transmission line to its corresponding peripheral terminal so that each peripheral terminal has an unimpeded exclusive line connection to its corresponding line control processor;
(d) a distribution-control means including:
(d1) message level interface means including logic means to connect a data path having a standard transmission discipline to said I/O translator interface of said main system, said message level interface operating to transfer a stream of char-acters without interruption until a complete mes-sage block is transferred;
(d2) means to signal said main system if an ad-dressed line control processor is busy;
(d3) means to signal said main system if an addressed line control processor is available, and to connect said addressed line control processor to said main system;
(d4) means, when a line control processor requests access, to connect said requesting line control processor to said main system, by activation of selected backplane transmission lines to said line control processor requesting access;
(d5) means for setting a local base priority value number for each line control processor within a given base module, and using said value number for determining priority of access when simulta-neous requests for access occur between line control processors in the same Base Module.

2. The Base Module of claim 1, wherein said distribution-control means includes:
(d6) means for setting a global priority value number for each line control processor to provide said input/output translator interface of said main system with data to determine precedence of access to memory among competing line control processors in different Base Modules.

3. The Base Module of claim 2, wherein said distribution-control means includes:
(d7) emergency request interrupt means when a line control processor is requesting access to memory, to provide a signal to said input/output translator with the topmost priority value number for that line control processor when lack of such access would result in an incomplete message transmission causing an access error.

4. The Base Module of claim 1, wherein said distribution-control means includes:
means for setting a global priority number signal for each line control processor;
means for connecting, when two or more line control processors is a Base Module simultaneously request access, the line control processor with the highest local priority number to said distribution-control means and then transmiting, to the said input/output translator interface, the global priority number for the connected line control processor.

5. The Base Module of claim 1, operating in connection with an additional second main system wherein each of said first and second ma m systems include an input/output translator interface which generates a line control processor address signal and a channel address signal for each I/O operation, said distribution-control means further including:
means, after receipt of a line control processor address signal and a channel address signal from said first or second main system to check for availability of the selected line control processor;

means to decode the line control processor address signal for activating the backplane transmission lines to said addressed line control processor;
means to signal the input/output translator interface of said main system that the addressed line control processor is now connected for data transfer;
second message level interface connection means to said second main system.

6. The Base Module of claim 5, wherein said distribution-control means includes:
means, when the said input/output translator interface requests connection to a specifically addressed line control processor, to check parity of the request signal and parity of the address signal, to check whether the addressed line control processor is available and thence to signal a response to the said input/output translator interface.

7. In a digital system for the transfer and control of digital information between a main system, which includes a processor with main memory having an I/O translator interface unit, and a plurality of remote peripheral terminal units, wherein each peripheral terminal unit is connected to the main system via a corresponding line control processor, and wherein groups of said line control processors at a given site are organized into Base Modules, a Base Module unit comprising:
(a) a plurality of line control processors, each of which has its own dedicated connection to a corresponding peripheral terminal unit and wherein each of said line control processors is adapted to handle the particular discipline required by its corresponding peripheral terminal unit, each of said line control processors including a data buffer memory having sufficient memory space for storing at least one complete message block of information data and complete control data, said control data including a command/descriptor word to control the type of operation, a descriptor link word to identify the particular input/output command involved, and a result descriptor work to inform the main system of completion of the command or error therein, (b) a single backplane common to each of said plurality of line control processors within said Base Module, said backplane including:
(b1) transmission lines from each line control processor to a distribution-control means, (b2) transmission lines from each line control processor to a maintenance card unit and a termination card unit;
(b3) a first exclusively dedicated line from each line control processor to said distribution-control means for emergency requests for access to the main system, (b4) a second exclusively dedicated line from each line control processor to said distribution control means for signaling the particular line control processor that is addressed by said main system;
(c) connection means for connecting of each said plurality of line control processors with a dedicated transmission line to its corresponding peripheral terminal so that:
each peripheral terminal has an unimpeded exclusive line connection to its corresponding line control processor.

(d) a distribution-control means including:
(d1) register means to receive the address of a selected line control processor from said main system;
(d2) decoding means to enable connection, via said backplane, of said selected line control processor to said main system;
(d3) gating means for controlling the connection or disconnection of said selected line control processor to said main system;
(e) maintenance card means connected to said backplane including:
(e1) a clock for supplying timing signals to each line control processor;
(e2) means for providing on-line diagnostic signals to any selected line control processor and for simulating the peripheral unit corresponding to each line control processor;
(e3) means to access said data buffer memory to check its operation;
(f) termination card means connected to said backplane including:
(f1) power supply means for each line control pro-cessor and said distribution control means;
(f2) termination impedance means to balance the transmission line impedances of each of the lines on said backplane;
(g) means for setting a local priority number signal for each line control processor in said Base Module, for selecting priority of access when access-requests occur simultaneously by two or more line control processors in that Base Module:

(h) message level interface means whereby said distrib-ution control means operates to transfer a stream of characters to or from said main system without interruption until a complete message block is transferred.

8. The Base Module of claim 7, wherein said distribution-control means includes:
first logic means to signal the main system of a previously addressed line control processor that the addressed line control processor is available or non-available, and to connect the addressed line control processor, when available, to said main system;
second logic means to signal the main system when a line control processor requests access and to connect, when said main system grants access, said line control processor to said main system.

9. The Base Module of claim 8, wherein said main system provides a command descriptor word to said line control processor and said line control processor includes:
execution logic means to execute said command descriptor word received from said main system; and a status count register having a count number which determines the sequence of logical operations to be followed by said execution logic means.

10. In a digital system for the transfer and control of digital information between a main system, which includes a processor with main memory having an I/O translator interface unit, and a plurality of remote peripheral terminal units, wherein each peripheral terminal unit is connected to the main system via a corresponding line control processor, and wherein groups of said line control processors at a given site are organized into Base Module unit comprising:

(a) a plurality of line control processors each of which is connected by a dedicated transmission line to its corresponding peripheral terminal unit and wherein each of said line control processors includes:
(a1) a data buffer memory having storage for a complete message block of data and a complete set of control words including I/O commands received from main memory;
(a2) logic means to execute said I/O commands and to control data transfers between said data buffer memory and said main system and/or its corresponding peripheral terminal unit;
(a3) register means for developing status condition signals to cause said logic means to actuate the sequential switching required to execute said I/O commands;
(b) distribution-control means including:
(b1) means to receive the channel number and the address of a selected line control processor;
(b2) means to check the availability of a selected line control processor, and if available, to connect said line control processor to said main system;
(b3) gating means to control the connections or disconnection of a selected line control processor to said main system;
(b4) means to provide an internal base priority signal for each line control processor and to connect the highest priority line control processor to the main system when two or more line control processors simultaneously request access;

(b5) means to provide a global priority signal, to said main system, for each line control processor requesting access to said main system;
(b6) message level interfaced means to said main system and operating to transfer a complete message block of data without interruption;
(c) a common backplane means providing transmission lines to and from each line control processor to said distribution-control means and including:
(c1) a dedicated address line from each line control processor to said distribution-control means;
(c2) a dedicated line for access-requests from each line control processor to said distribution-control means;
(c3) connection means from each line control processor to a maintenance unit means and to a termination unit means:
(d) a common maintenance unit means connected to each line control processor for simulating each peripheral terminal and testing the operation of each line control processor.
(e) a common termination unit means connected to said backplane means for providing line termination impedances, and power to each of said line control processors.

11. The Base Module of claim 10, wherein said line control processor includes:
(a) means, when said data buffer memory is either full or empty, for signaling an emergency request for access to said distribution-control means will generate the top priority number access-request signal for transmittal to said main system.