CA1085061A - Transistor with emitter of high and low doping - Google Patents

Transistor with emitter of high and low doping

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Publication number
CA1085061A
CA1085061A CA277,047A CA277047A CA1085061A CA 1085061 A CA1085061 A CA 1085061A CA 277047 A CA277047 A CA 277047A CA 1085061 A CA1085061 A CA 1085061A
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CA
Canada
Prior art keywords
region
layer
silicon
conductivity type
micron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA277,047A
Other languages
French (fr)
Inventor
Hendrik C. De Graaff
Paul A.H. Hart
Albert Schmitz
Jan W. Slotboom
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
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Application granted granted Critical
Publication of CA1085061A publication Critical patent/CA1085061A/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special

Abstract

ABSTRACT:
A method of manufacturing a semiconductor device having a transistor structure of which the emitter zone comprises a lower-doped region ad-joining the base zone and a more highly-doped re-gion adjoining the surface. According to the in-vention, said more highly-doped part is obtained by the introduction of doping atoms via an undop-ed polycrystalline layer provided on the surface.
Preferably a thin silicon nitride or silicon oxide layer is provided between the surface and the poly-crystalline silicon layer prior to providing the latter,

Description

108S06~

The invention relates to a method of manufacturing a semiconductor device having a tran-sistor, in which method there is started from a semi-conductor body having a first region of a first con-ductivity type on which a second region of the second conductivity type is provided, on which second re-gion a third region of the first conductivity type is provided, after which a surface-adjoining fourth region of the first conductivity type which has a higher doping than the third region is provided in the third region, the first region forming the col-lector zone, the second region formi.ng the base zone and the third and fourth regions forming the emitter -~
zone of a bipolar transistor.
The invention also relates to a semicon-ductor device manufactured by using the method. ~-A method of manufacturing a semiconductor device having a transistor as described above is dis-closed in United States Patent Specification 3,591,430, E.S. Schlegel, July 6, 1971. The transistor described in said Specification comprises an emitter zone which consists of a comparatively low doped part which ad-joins the emitter-base junction, and a comparatively highly doped part which adjoins the surface
- 2 -... . ~ .

~0 850 6 ~ 30.3.77 and forms a PP or an NN junction with the lower doped part. -It has been found that such a transistor can show very good properties, in particular a low noise, and also a high current amplification. Fur-thermore, when the collector zone comprises a lower-doped part adjoining the collector-base junction and a more highly doped part adjoining said lower-doped part, such transistor structures may show a rather symmetrical (N NPNN or P PNPP ) structure of which the symmetry properties can advantageously be used in many circuit arrangements. The transistors des-cribed may be used either as a discrete transistor or be used in an integrated circuit, in which lat-ter case the collector zone can be formed entirely or partly by a buried layer of the first conducti-vity type. Therefore the semiconductor device ac-cording to the invention may consist of an integrat-ed circuit having a transistor as described above.
The highly doped surface-adjoining part of the emitter zone, hereinbefore referred to as the "fourth region", can be manufactured in dif-ferent manners, for example, by diffusion from the gaseous phase or by ion implantation, the result-ing s~rface doping being sufficiently high, for example, in an N+N emitter 10 9 to 10 1 atoms per cm .

-'~ OBS061 30 One of the objects of the invention is to provide a method of manufacturing such a transistor having considerably improved electrical properties, in particular having a considerably better current amplification, by which is to be understood a higher and/or a less current-dependent current amplification.
The invention is inter alia based on the recognition of the fact that this object can be achieved by providing the highly doped surface layer of the emi.tter zone according to a very spe-cilic method.
Actually Applicants have found that the way in which the highly doped emitter-surface layer is provided is of very great importance for the pro-perties of the transistor described, which was not to be expected since the highly doped emitter sur-face layer itself does not adjoin the base zone but . .
is separated therefrom by the low-doped part of the emitter zone (the "third region").
According to the invention, a method of the kind described in the preamble is therefore characterized in that, in order to form the fourth region, an undoped layer of polycrystalline silicon is provided on the third region after which the fourth region is formed in the third region by the introduction of a dopant through the poly-_ 4 :
3-3-77 ~o8506~

crystalline silicon layer.
It is to be noted that the formation of an emitter zone by diffusion via a polycrystalline si-licon layer was known ~_ se for high-frequency transistors, see for example H.Murrmann and A.Glasl "Der Polysil-Emitter" 6th International Congress on Microelectronics, Munich, 25-27 Novem-ber, 1974. However, in contrast with the invention, in this known method the whole emitter zone adjoin-ing the base zone is provided in this manner. As yet it is not quite obvious why this rnethod re-sults in the said considerable improvements in transistors having ~.n N~N or P~P emitter in which the highly doped emitter region is situated at a distance from the base zone. It has been found, however, that the emitter efficiency of transis-tors obtained by using the method according to the invention lies considerably higher than that of the described known transistor structures of which the highly doped emitter surface la~er was manu-factured in a different manner~
Furthermore it is of importance to note that the term polycrystalline silicon in this ap-plication is used in a wide sense for non-mono-crystalline silicon so that a polycrystalline layer is to be understood to mean herein not only a layer consisting of lareer or mal~er regions .

3.3.77 ~08S06~

which in themselves are monocrystalline but also a layer haviDg an amorphous structure in which no se-parate regions with in themselves regular atomic arrangement are to be distinguished.
It has furthermore been found that parti-cularly favourable results are obtained when a thin layer of electrically insulating material is pro-vided on the third region prior to providing the layer of polycrystalline silicon. The reason why such a layer yields such a favourable result i5 still unknown. Advantageously, a layer is provided in a thickness of at least 0.0010 micron (10~) and at most 0.0100 micron (100~), preferably of at least 0.0020 micron (20~) and at most o.oo60 micron (60~). Silicon nitride and silicon oxide have prov-ed particularly favourable as a material for said layer. In this connection "silicon nitride" is to be understood to mean a layer whlch contains sili-con, nitrogen and in most cases also a certain quantity of oxygen, but of which the content of nitrogen is sufficiently high for being used, if desired, as an anti-oxidation mask. Likewise in this connection "silicon oxide" is to be understood to mean a layer which contain silicon and oxygen in a ratio which does not necessarily correspond to that in ~iO2 (silicon dioxide), for example a mixture of SiO2 and SiO.

3.3.77 108506~

The invention will now be described in groater detail with reference to an eMbodin1ent and the drawing, in which Figs. 1 to 7 are diagrarnmatic cross-sectional views of successive stages in the manufacture of a semiconductor device according to the invention, and Fig. 8 shows another embodiment of a de-vice manu~actured according to the invention.
The figures are diagrammatic and aré not drawn to scale. Corresponding components in the fi-gures are referred to by the sa~e reference nu-merals. Semiconductor zones of the same conducti-vity type are shaded in the same direction. In so far as process steps to form semiconductor regions and insulating layers on the upper side of the se-miconductor body also give rise to the formation of layers on or in the lower side, said layers or zones which are removed afterwards and are of no significance for the invention are not shown in the figures. Although the manufacture of only one device is shown, a large number of such de-vices which can be separated from each other after-wards are generally manufactured simultaneously in the same semiconductor wafer.
Figs. 1 to 7 are diagrammatic cross-sec-tional views of successive stages of the method according to the invention in which the starting PIIN ~372 ~08506~

material i9 a semiconductor body 1 having a first re-gion (2, 3) of a first conductivity type. The start-ing material in this example is a semiconductor body of silicon, while the region (2, 3) is n-type conduc-tive. Ilowever, there may also be started from a dif-ferent semiconductor material, for example germanium or a III-V compound, for example Ga As.
A second region 4 of the second conducti-vity type, so in this example a p-type conductive region, is provided on said first region 2, 3). The first region (2, 3) is obtained in this case by growing on a substrate 2 o~ n-type silicon having a resisti.vity of 0,005 to 0.01 Ohm.cm an epitaxial layer 3 of n-type silicon having a resistivity approxi~ately o.6 Ohm.cm and a thickness of ap-proximately 10 microns in a manner conventionally used in semiconductor technology. Said layer is then oxi i~ed thermally so that a layer 5 of sili-con oxide is formed, approximately 0.5 micron thick.
While using known photo-lacquer and etching methods, a window 6 is etched in said layer in dimensions of, for example~ 100 x 100 microns~ after which a very thin oxide layer 7, for example, 0.05 mi-cron thick, is formed in said window by a short thermal oxidation. Boron ions having an energy of, for example, 70 keV and a dose of, for example 10 3 atoms per cm are then implanted in the layer Pl~ 8372 ` lOBS06~ 30.3.77 3 through said thin oxide layer 7. By heating, for example first at 900C for 30 minutes in dry nitro-gen and then at 1200 for 2 hours in an oxidizing atmosphere, the second region 4 is obtained in the form of a p-type layer having a sheet resistance ~ s of approximately 10 to 30 kOhm per square.
However, the second region 4 may also be formed differently, for example by diffusion from the gaseous phase, from a doped layer, by epitaxial growth or differently. Thus the situation sho~n in Fig. 1 is obtained.
A third region 8 of the first (n) conduc-tivity type is then provided on the second region
4, see fig. 2. For that purpose the whole silico~
surface is etched clean and a layer 8 of n-type silicon having a thickness of approximately 4 microns and a resisti~ity of approximately o.6 Ohm.cm is obtained by epitaxial growth according to known methods. The layer 4 has such a low dop-ing that it hardly diffuses in the layer 8. In order to be able to contact the region 4 after-wards, a highly doped ~type annular zone 9 is diffused after the growth of the layer 8 in known manner through the layer 8. An oxide layer 10 is formed.
A surface-adjoining fourth region 11 of the first conductlvity type, so in this case g ` 1085061 30.3 77 an n-type region, is then provided in the third re-gion 8 with a higher doping than the third region 8~ the first region (2, 3) forming the collector zone, the second region 4 forming ~he base zone, and the third region 8 with the fourth region 11 forming the emitter zone of a bipolar transistor, as is shown in Fig. 7 which i5 a cross-sectional view through the ultimately obtained device.
According to the invention, in order to form said fourth region on the third region 8, an undoped layer 12 of polycrystalline silicon is provided (see ~ig. 5) after which the fourth re-gion 11 is formed in the third region through the polycrystalline silicon layer 12 by the introduc-tion of a dopant, in this example a donor. In this example this is done as follows.
First an aperture is etched in the oxide layer at the area of the fourth region 11 to be provided.
Advantageously, first a very thin insu-lation layer is provided on the surface of the layer 8 in the aperture (after a HF-dip, for exam-- ple 30 seconds in a 1% HF-solution). This may be, for example, a silicon nitride layer. This may be provided by heating in an atmosphere containing nitrogen and ammonia in a ratio of 1 volume NH3 on 20 volumes of N2, at a temperature between ap-~0 8 ~ 6 ~ 3.3.77 //oo ~
i" proximately 900 C and ~ , for example at 1000 C, for 30 minutes. An approximately 0.004 micron ( 40 ~) thick layer 19 is formed on the layer 8 (see Fig. 3) which contains oxygen in addition to silicon and ni-trogen, but of which the content of nitrogen proves to be sufficiently high for it to be used as an anti-oxidation mask. The layer 19 is shown in Fi-gure 3 but lS not shown in Figs. 4 - 7 and 8 for reasons of clarity. The- silicon nitride layer 19 may also be provided differently, for example in a nitrogen plasma, operated at radio frequency, f`or example with a power of 600 W~for 60 minutes at a pressure of 3 Torr, or in an ammonia (NH3) plasma.
Instead of silicon nitride, the layer 19 may be silicon oxide. It may be provided by thermal oxidation at high temperature (700 - 800 C) or by exposure to an oxygen plasma (in which, for exa~ple, at will layers of 0.0025 to 0. oo60 mi-cron can be obtained with powers varying from 100 to 400 W and times varying from 15 to 30 minutes).
Alternatively, such a layer can be ob-tained by a treatment in smoking and concentrated boiling nitric acid, respectively.
After providing the layer 19 an undoped layer 12 of polycrystalline silicon is provided, for example, by chemical conversion of SiH4 at ap-.

, ~ ~

1085061 30.3.77 -proximately 650 C. The layer 12 has a thickness of, for example, 0.5 micron. In order to ~ve the layer 12 the desired shape, a very thin surface layer of the layer 12 is converted by thermal oxidation into an oxide layer 13 which is etched into the desired shape by means of a HF-containing solution and then serves as an etching mask for etching the poly-crystalline layer 12. Etching of the layer 12 may be done with known etchants, generally a liquid containing HN03, HF and acetic acid. In this man-ner the structure shown in Fig. 4 is obtained. Af-ter a dip etch, in which no mask is necessary, to remove the thin oxide layer 13 the structure shown in Fig. 5 is obtained.
A donor, in this example phosphorus, is then introduced in the region 8 via the undoped high-ohmic layer of polycrystalline silicon 12.
In this example-this is done by heating in a POCl3-containing atmosphere at 880C for approximately 20 minutes succeeded by an oxidation in moist nitrogen (approximately 20 minutes at 800). Dur-ing this treatment the phosphorus diffuses through the polycrystalline silicon layer 12 in the region 8 and forms therein a very shallow highly-doped n-type layer 11 having a thickness which is smal-ler than 0.1 micron. The polycrystalline silicon layer 12 is further strongly doped with phosphorus . , . - ~' ' . ' . : , .:
. .
.

108S06~ 30.3.77 during this process, while a phosphor-glass layer 14 is formed over the assembly. Contact windows are then etched in the usual manner in said phosphor-glass layer after which, by vapour-depositing a metal layer, for example an aluminium layer~ and etching, a base contact layer ~5 is formed on the annular zone 9 and an emitter contact layer 16 is formed on the polycrystalline silicon layer 12 After removing all the glass layers and diffusion layers formed on or in the lower side of the sili-con plate during the preceding process steps, a collector contact layer 17 is provided on said lower side.
In this example the fourth region 11 is provided in the semiconductor body down to such a depth that the distance from the junction 18 be-tween the third region 8 and the fourth region 11 down to the second region 4 is at most a diffusion length of minority charge carriers (so in this exam-ple holes) in the third region 8. As a result of this a high current gain factor is obtained, Ad-vantages, notably a large current independence of the current gain factor, are achieved by the method according to the invention also when the said distance is larger than a diffusion length, although the current gain factor itself then is smaller.

- . ~. . . ..

PHN ~372 3.3.7~

The transistors manufactured according to the described process had a very good current gain, which appears from the measured emitter-Gummel num-bers (GE) which varied from 5.10 3 sec.cm to 10 sec.cm . The emitter-Gummel number is to be understood to mean GE = hFE x GB, where hFE is the current gain factor and GB is the base-Gummel num-ber; GB is defined as GB = BD B , where WB = the base width in cm, NB = the base doping in atoms per cm3, and DN = the diffusion coefficient for electrons in the (p-type) base in cm2.sec 1. For these definitions and the meaning hereof for the behaviour of the transistor, reference is invited, for example, to H.C. de Graaf and J.W. Slotboom, Solid State Electronics, Vol. 19, 1976, pp.
809 - 814.
Since the starting material in this exam-ple was a semiconductor body of which the first re-gion was formed by a highly doped substrate on which a lower doped epitaxial layer of the same conductivity type was grown, an N NPNN structure is formed which may show useful symmetry proper-ties. However, the collector region may also be formed differently, for example as a homogeneous-ly doped region without an epitaxial layer. The first region (2, 3) may alternatively consist, for example in integrated circuits, of an "island"

_ 14 :: , . . ~ .

1085~ PHN 8372 3.3.77 2 having a buried layer 3 which are surrounded en-tirely by a p-type conductive region 20. See Fig. 8 in which such an integrated transistor is shown as an example and is provided in a p-type substrate 20 beside a p-n diode (21, 22) provided in another n-type island 21.
In the example of Figs. 1 to 7, phos-phorus atoms were diffused through the polycrystal-line layer 12. The introduction of doping atoms through the polycrystalline silicon layer 12, however, may also often be carried out advanta-geously by ion implantation in the direction of the arrows shown in Fig. 5 in which the glass layer 14 is not formed. Prior to or after such an implantation an insulating layer, for example of silicon oxide, may be formed indeed over the surface, in which layer the contact windows are provided afterwards. In so far as such a layer is provided prior to the implantation, it should, of course, be thin enough to enable implantation of doping ions through said insulating layer and through the polycrystalline layer.
It is to be noted that the introduction of the doping atoms via the polycrystalline sili-con layer may alternatively be carried out in two steps, for example, by ~rst diffusing or implant-ing doping atoms in the undoped polycrystalline .

1085061 30 3 j7 layer and then diffusing at least a part of said doping atoms from the polycrystalline silicon layer in the region 8 illa second step by heating. Alter-natively, instead of from the gaseous phase~ the dopant may be provided in the fourth region from a doped layer, for example, a doped glass layer or another doped layer, through the original un-doped polycrystalline silicon layer.
Furthermore, many variations may be ap-1~ plied to the method described, In particular, the conductivity types of all the semiconductor re-gions in the examples may (simultaneously) be changed and other insulating layers, for example of aluminium oxide or silicon nitride, and other semiconductor materials may be used. Different semiconductor materials separated by hetero junctions may also be used. Other doping atoms may also be used, for example instead of phosphorus another donor and instead of boron another acceptor.
- The transistor described may alternative-ly form part of a complicated device, for example a thyristor. For example, the p-type region 20 in Fig. 8 may be contacted so that a pnpn thyristor (20, 3, 2, 4, 8, 11) is formed.

'

Claims (17)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS
1. A method of manufacturing a semiconductor device having a transistor, in which the starting .
material is a semiconductor body having a first region of a first conductivity type on which a second region of the second conductivity type is provided, on which second region a third region of the first conductivity type is provided, after which a surface-adjoining fourth region of the first con-ductivity type which has a higher doping than the third region is provided in the third region, the first region forming the collector zone, the se-cond region forming the base zone, and the third and fourth regions forming the emitter zone of a bipolar transistor, characterized in that, in or-der to form the fourth region an undoped layer of polycrystalline silicon is provided on the third region after which the fourth region is formed in the third region by the introduction of a dopant through the polycrystalline silicon layer.
2. A method as claimed in Claim 1, charac-terized in that a thin layer of an electrically insulating material is provided on the third re-gion prior to providing the layer of polycrystal-line silicon.
3. A method as claimed in Claim 2, characterized in that a thin layer is provided in a thickness of at least 0.0010 micron (10 .ANG.) and at most 0.0100 micron (100 .ANG.).
4. A method as claimed in Claim 2, characterized in that a thin layer is provided in a thickness of at least 0.0020 micron (20 .ANG.) and at most 0.0060 micron (60 .ANG.).
5. A method as claimed in Claim 2, characterized in that a thin layer of silicon nitride is provided.
6. A method as claimed in Claim 5, characterized in that the layer of silicon nitride is provided by heat-ing in an atmosphere containing nitrogen and ammonia.
7. A method as claimed in Claim 5, characterized in that the layer of silicon nitride is provided in a nitrogen plasma or an ammonia plasma.
8. A method as claimed in Claim 2, characterized in that a thin layer of silicon oxide is provided.
9. A method as claimed in Claim 8, characterized in that the layer of silicon oxide is provided by ther-mal oxidation.
10. A method as claimed in Claim 8, characterized in that the layer of silicon oxide is provided in an oxygen plasma.
11. A method as claimed in Claim 1, characterized in that the fourth region is provided in the semicon-ductor body down to such a depth that the distance from the junction between the third and the fourth region down to the second region is at most a dif-fusion length of minority charge carriers in the third region.
12. A method as claimed in Claim 1, characterized in that the third region is formed by the epitaxial growth on the second region.
13. A method as claimed in Claim 1, characterized in that the semiconductor body consists entirely of silicon.
14. A method as claimed in Claim 1, characterized in that the regions of the first conductivity type are n-type conductive.
15. A method as claimed in Claim 1, characterized in that starting material is a semiconductor body of which the first region is formed by growing on a highly doped substrate of the first conductivity type an epitaxial layer of a lower doping of the first conduct-ivity type, on which epitaxial layer the second and third regions are then provided.
16. A method as claimed in Claim 1, characterized in that the dopant is diffused through the polycrystal-line silicon layer.
17. A method as claimed in Claim 1, characterized in that the dopant is implanted through the polycrystal-line layer.
CA277,047A 1976-04-27 1977-04-26 Transistor with emitter of high and low doping Expired CA1085061A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL7604445A NL7604445A (en) 1976-04-27 1976-04-27 PROCESS FOR MANUFACTURE OF A SEMI-CONDUCTED DEVICE, AND DEVICE MANUFACTURED BY APPLICATION OF THE PROCEDURE.
NL7604445 1976-04-27

Publications (1)

Publication Number Publication Date
CA1085061A true CA1085061A (en) 1980-09-02

Family

ID=19826076

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CA277,047A Expired CA1085061A (en) 1976-04-27 1977-04-26 Transistor with emitter of high and low doping

Country Status (8)

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US (1) US4151006A (en)
JP (1) JPS52139386A (en)
CA (1) CA1085061A (en)
DE (1) DE2718449A1 (en)
FR (1) FR2349955A1 (en)
GB (1) GB1522291A (en)
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JPS6112388B2 (en) 1986-04-08
IT1078440B (en) 1985-05-08
FR2349955B1 (en) 1983-06-17
DE2718449A1 (en) 1977-11-10
JPS52139386A (en) 1977-11-21
NL7604445A (en) 1977-10-31
DE2718449C2 (en) 1987-11-26
GB1522291A (en) 1978-08-23
US4151006A (en) 1979-04-24
FR2349955A1 (en) 1977-11-25

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