CA1078524A - Destination selection apparatus for a bus oriented computer system - Google Patents
Destination selection apparatus for a bus oriented computer systemInfo
- Publication number
- CA1078524A CA1078524A CA263,608A CA263608A CA1078524A CA 1078524 A CA1078524 A CA 1078524A CA 263608 A CA263608 A CA 263608A CA 1078524 A CA1078524 A CA 1078524A
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- CA
- Canada
- Prior art keywords
- local bus
- busy
- destination
- bus adapter
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Hardware Redundancy (AREA)
Abstract
Title of the Invention DESTINATION SELECTION APPARATUS FOR A
BUS ORIENTED COMPUTER SYSTEM
Abstract of the Disclosure In order to carry out data transfer among the sub-systems of a bus oriented data processing system, each sub-system is coupled to the bus by a local bus adapter which con-trols both source and destination aspects of the information transfer. Each local bus adapter has a unique "busy" line which may be interrogated by any local bus adapter connected to the bus. When a source subsystem wishes to transfer information to a destination subsystem, the source local bus adapter determines from the destination local bus adapter's busy line whether or not the destination subsystem is available to accept the informa-tion. If the destination subsystem is available, the source local bus adapter requests access to the bus from priority reso-lution apparatus. When the source request is granted, the source local bus adapter issues the message to the bus and also sets the destination local bus adapter's busy line to designate the busy state which indicates to the destination bus adapter that it must prepare to receive a message and also indicates to all subsequently requesting local bus adapters that the particu-lar subsystem to which information just placed on the bus is to be transferred is temporarily not available to receive informa-tion from any other local bus adapter. When the message has been received by the destination local bus adapter, both the source and destination local bus adapters enter a status cycle to check the integrity of the transmitted massage. If the message is received intact, both the source and destination local bus adapters complete their individual housekeeping tasks during which the destination local bus adapter tuns off its busy line. If an error has occurred during the message transmission, the destination subsystem, after the transfer has been retried once, disregards the message and turns off its busy line.
BUS ORIENTED COMPUTER SYSTEM
Abstract of the Disclosure In order to carry out data transfer among the sub-systems of a bus oriented data processing system, each sub-system is coupled to the bus by a local bus adapter which con-trols both source and destination aspects of the information transfer. Each local bus adapter has a unique "busy" line which may be interrogated by any local bus adapter connected to the bus. When a source subsystem wishes to transfer information to a destination subsystem, the source local bus adapter determines from the destination local bus adapter's busy line whether or not the destination subsystem is available to accept the informa-tion. If the destination subsystem is available, the source local bus adapter requests access to the bus from priority reso-lution apparatus. When the source request is granted, the source local bus adapter issues the message to the bus and also sets the destination local bus adapter's busy line to designate the busy state which indicates to the destination bus adapter that it must prepare to receive a message and also indicates to all subsequently requesting local bus adapters that the particu-lar subsystem to which information just placed on the bus is to be transferred is temporarily not available to receive informa-tion from any other local bus adapter. When the message has been received by the destination local bus adapter, both the source and destination local bus adapters enter a status cycle to check the integrity of the transmitted massage. If the message is received intact, both the source and destination local bus adapters complete their individual housekeeping tasks during which the destination local bus adapter tuns off its busy line. If an error has occurred during the message transmission, the destination subsystem, after the transfer has been retried once, disregards the message and turns off its busy line.
Description
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Field of the Invention This invention relates to the data processiny arts and, more particularly, to the art of information transfer among the subsystems of a bus oriented information data processing system.
Background of the Invention Among the recognized architectures for data processing syfitems is the well known bus oriented system in which the various subsystems communicate with one another through a common bus.
In bus oriented systems, it is necessary for a source subsystem to ascertain the availability of and obtain the attention of the destination subsystem. In the prior art, this function has typ-ically been carried out using the so-called "broadcast" technique in which the source subsystem places the address of the destina-tion subsystem on address lines constituting a section OL the common bus. The destination subsystem must respond with a "hand-shake" message, the source subsystem may then proceed to request access to the bus for the purpose of transmitting the message.
The broadcast technique, of course, has many variants, but the common thread among them is the necessity for the issuance of a preliminary inquiry from the source to the destination and a definite response from the destination to the source before actual information transfer can commence.
Those skilled in the art will appreciate that an in-crease in system speed could be obtained if the necessity for the preliminary addressing and acknowledgment dialog between source and destination subsystems could be eliminated.
Objects of the Invention It is therefore a broad object of our invention to provide an improved means for selecting a destination subsystem by a source subsystem to effect information transfer in a data processihg subsystem.
It is another object of our invention to provide such
Field of the Invention This invention relates to the data processiny arts and, more particularly, to the art of information transfer among the subsystems of a bus oriented information data processing system.
Background of the Invention Among the recognized architectures for data processing syfitems is the well known bus oriented system in which the various subsystems communicate with one another through a common bus.
In bus oriented systems, it is necessary for a source subsystem to ascertain the availability of and obtain the attention of the destination subsystem. In the prior art, this function has typ-ically been carried out using the so-called "broadcast" technique in which the source subsystem places the address of the destina-tion subsystem on address lines constituting a section OL the common bus. The destination subsystem must respond with a "hand-shake" message, the source subsystem may then proceed to request access to the bus for the purpose of transmitting the message.
The broadcast technique, of course, has many variants, but the common thread among them is the necessity for the issuance of a preliminary inquiry from the source to the destination and a definite response from the destination to the source before actual information transfer can commence.
Those skilled in the art will appreciate that an in-crease in system speed could be obtained if the necessity for the preliminary addressing and acknowledgment dialog between source and destination subsystems could be eliminated.
Objects of the Invention It is therefore a broad object of our invention to provide an improved means for selecting a destination subsystem by a source subsystem to effect information transfer in a data processihg subsystem.
It is another object of our invention to provide such
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means which is simple and completely reliable in oper~tion.
It is yet another object of our invention to provide such means by which the selection function is carried out ex-tremely quickly and reliably.
In a more specific aspect, it is an ob~ec-t of our in-vention to provide means by which a fundamental subsystem status, busy or not busy, is available to, and controllable by, the local bus adapters of all the other subsystems in the system.
It is a still further object of our invention to pro-vide means by which a destination subsystem can respond to actiontaken at a source local bus adapter to prepare to receive a valid message from the source subsystem.
Brief Description of the Invention Briefly, these and other objects of the invention are achieved in a data processing system apparatus for establishing a data transmission path between an originating data processor and a destination data processor. The apparatus comprises a common bus, a first local bus adapter operatively connected be-tween the originating data processor and the common bus, and a second local bus adapter operatively connected between the desti-nation data processor and the common bus. Both the first and second local bus adapters include a busy indicator means having a busy state providing an indication that the data processor coupled to said local bus adapter is busy, a means for setting the busy indicator means of the second local bus adapter to the busy state in response to a request signal from the first local bus adapter, and a means responsive to the busy state of the busy indicator means for accep-ting data from the common bus.
When one subsystem wishes to communicate wi-th another subsystem, a request is issued to the originating or source sub-system's local bus adapter along with the identi~icat.ion of the prospective destination subsystem. I'he source local bus adapter )7 ~
internally lnterrogates the busy lndicator means or busy line of the prospective destination subsystem, and if the destin3tion subsystem is not busy, the source local bus adapter issues a re-quest for access to the bus to bus control clrcuitryO If the source subsystem is the highest priority subsystem curren~ly making a request for the bus, the request is granted. In re-spo~se, the source local bus adapter sets the indicator means of the destination local bus adapter to the busy state which in-dicates to the dest~nation local bus adapter that it must prepare to receive a ~essage off the bus and also indicates to all other prospectiv~ source subsystems tha~ the selected destinatlon sub-system is temporarily unavailable to themO After the message is transmitted, both the source and destin~tion local bus adapters enter a status cycle to check the lntegrity of the transmitted messageO Thereafter, the destination subsystem resets its own indicator means and once again beco~es available ~o accept a subsequent me~sage from any local bu~ adapter which m2y be able to set its indieator means.
The subject matter of the ~nvent~on is particularly pointed out and distinctly claimed in the concluding por~ion of the speclficationO The invention, however, both as to organiza~
tion and method of operation, may best be understood by reference to the following description ~aken in connection with the sub-joined claims and the accompanylng drawings of which:
Figure 1 is a major block diagram of a bus oriented data processing system comprisi~g an exemplary environment in which our invention ~inds use;
Figures ~A and 2B, taken to~ether, are a logic block diagram of a local bus adapter module from the system of Flgure l;
Figure 3 is a detailed logic cliagr~m of a one~of-~lx~
~een decoder repre~e~ted a~ a logic block ln Flgure 2;
Figures 4A and 4B, taken together, are a detailed ~ .. .. .
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logic diagram of busy line selection logic represen~ed ~s a loglc block ln Flgure 2, Figures 5A and 5B 7 ta~en together, are a logic diagram of priority determination selection logic which is contained within the bus control major logic block of Figure l;
Figure 6 illustrates simple clock and timlng pulse derivation logic by which the sign~ls necessary to coordinate the orderly sequential operation of the system are obtained; and Figure 7 is a~ event sequence flow diagram which illus-trates the operation and ~nteraction of the various sy~tem con~stituents by which information ~ransfer is ~arried out according to our invent ion O
Detailed Description of the Apparatus The logic diagrams are present~d ln slightly simpli-fied form in order that the inventive roncept may be more readily understood. For example, instan~aneous response tlm2s are as-sumed such that no specia 1 circuitry is shown for overcoming logic race conditions which may occur as the speed of operation is increased until the circuits cannot be assumed ~o respond ~m-mediately~ The changes and additions required to overcome loglcrace conditions and other problems associated with extremely high speed operation are known to all skilled in the art and are of no consequence to an understandlng of the invention. To fur-ther clarify the inventive concepts, the logic is presented using the most basic types of AND-gates, OR-gates, flip-flops, etc. It ~s apparent that the inventive concepts can be realized and practiced utilizing the more complex types of logic elements which are now generally incorpora~ed into contemporary data pro-cessing sys~ems becau~e of the availabillty and general use of integrated circuits directly reallzing such complex logic ele-ments. Further, the operation of the apparatus ls presented in sz~
a strictly sequential form. Of cour9e, co~vent~onal t-lming practice in data processing appara~us u~illzes, to the ~ullest extent possible, overlapping and simultaneous logic operations to increase overall speed. I~ is believed that the invention would be obscured by the inclusion of all the logic in its most complex form of the exact machine embodiment in which the inven-tion is currently practiced.
A~tention is now directPd ~o Figure 1 which illustrates, in a block diagram, an exemplary data processing system in which the pre~ent invention flnds use. The data processing system of Figure 1 is bus oriented in that all the subsystems, including the processor subsystem 1, are coupled to one another by means of an internal transfer bus 2. The internal transfer bus is incor-poxated into an internal transfer bus subsystem 3 which also in-cludes a plurallty of local bus adapters 4, an interbus communi-cation adapter 5, bus control loglc 6, and timing logic 7. In the internal transfer subsystem to be described, up to 16 local bus adapters and interbus communicatlon adapters may be coupled to the internal transfer bus 2. Typically, only one interbus communication adapter 5 is provided. Undesignated subsystems 8 may constitute any of the subsystems or data processors usually found in a bus-orLented data processing system;~
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e.g.: core memory, tape units, disk units, printers, video dis-plays, etc. The service subsystem 9 may include a system console to effect two-way communication between an operator an~ the data processing system.
The function of the internal transfer bus 2 is to trans-mit information from one local bus adapter to another local bus adapter. It defines the paths and procedures to be used by the local bus adapters to communicate with each other. All informa-tion is passed over the internal transEer bus sequentially fol-lowing the common procedure defined by the internal transfer busprotocol. The identical local bus adapters 4 interface every subsystem to the internal transfer bus. Each local bus adapter performs all the logic operations necessary to insure that the internal transfer bus discipline is maintained at all times.
The bus control logic 6 performs several functions. Of most direct interest to the present invention, it arbitrates all local bus adapter reques-ts to use the internal transfer bus.
This is accomplished on a fixed priority basis in the exemplary embodiment. Each local bus adapter is assigned a specific pri-ority, and in case of simultaneous requests, the bus control honors the local bus adapter having the highest priority. The bus control logic also checks the parity of all messages sent over the internal transfer bus and reflects the result of the parity check onto the internal transfer bus for analysis by the communicating local bus adapters. The bus control logic can com-municate with the service subsystems 9 and the processor sub-system 1 by means of the serial service bus 10 in order to pro-vide certain system condition history and status information and signals of no direct consequence to the present invention.
The internal transfer subsystem is a synchronous logic machine in that all operations in the internal transfer subsystem are synchronized with clock and phase signals emanating from the ~;371~S~
~iming logic 7.
Referring now to Figures 2A and 2B, the apparatus com-prising an exemplary local bus adapter will be discllssed. The local bus adapter is disposed between a subsystem interface 11 and an internal transfer bus interface 12. The local bus adapter receives request, data~ destinatlon, and status information from its associated subsystem at the interface 11. Those skilled in the art will appreciate that such information is routinely avail-able from typical subsystems used in bus oriented data processing systems. The local bus adapter receives data, opcode, busy line, request-granted, and parity error information from the bus inter-face 12. The data and opcode information is selectively passed on to the subsystem. Similarly, the data and destination infor-mation received from the subsystem is selectively issued to the bus interface 12. In addition, the local bus adapter can issue a Request signal to the bus and also can affect the status of any one of the busy lines brought into the local bus adapter.
Data and destination information from the subsystem interface 11 is applied to an output buffer 13 and clocked into the buffer when the Subsystem Request flip-flop 19 is set. This same data and destination information is taken from the ou-tput buffer and applied to an output AND-gate array 14. Transfer of this information through the output AND-gate array 14 is control-led by the state of a Request Granted flip-flop 15 which has its ~ output connected to each of the gates in the array. The desti-nation code from the output buffer 13, which in the exemplary em-bodiment constitutes a 4 bit code designating ports 0000 through 1111 (i.e., 0 through 15), is applied to a one-of-sixteen decoder 16. One-of-sixteen decoder 16, which is described in detail be-low, issue~s an enabling signal ~rom a single one of its sixteenoutputs according to the binary configuration oE the input desti-nation code. The sixteen output lines from one-of-sixteen decoder 16 are applied to busy line selection logic 17 which also receives an input from the Q output of the Request Granted flip-flop 15. The busy lines 18 of all the subsystems in the system are also available for monitoring by the busy line selection logic 17. The busy line selection logic 17, which will be de-scribed in detail below, also includes means for selectively forcing any one of the busy lines 18 to the busy state.
A Request signal received from the subsystem interface 11 passes through a time controlled AND-gate 98 and is used to set the Request flip-flop 19. The Q output from the Request flip-flop 19 is applied as one input to an AND-gate 20, and, as previously noted, to the in-clock input to the output buffer 13.
The other input to the AND-gate 20, which serves to issue a priority request signal from the local bus adapter to the bus interface 12, is received from the busy line selection logic 17.
Information received from the bus interface 12 is gated to an input buffer 22 through an input AND-gate array 23 when a Busy flip-flop 21 is in the set state because the Q output there-from is coupled to enable the gates in the array 23. The ~ out-put from the Busy flip-flop is also applied to the set input of a Busy Line Latch flip-flop 96, and the Q output from the Busy Line Latch flip-flop is connected to the immediate local bus adapter's own busy line 97. Thus, once set, the Busy Line Latch flip-flop 96 holds the corresponding busy line in the busy state until the Busy Line Latch flip-flop is subsequently reset. The manner in which another local bus adapter raises the busy line 97 to set the Busy flip-flop 21 will be discussed below.
At the end of a message transmission cycle, a status check is carried out to determine the val:idity oE the received message. If the message is unacceptable to the receiving sub-system (such as including the opcode of a command which the particular subsystem is incapable of executing), the subsystem provides a corresponding signal to the status logic 24. Similar-ly, if a parity error i5 detected by the bus control logic 6 (Figure 1) a parity error signal is applied to the status logic 24. Thus, either type of error will be sensed by the status logic which also has the facility for determining whether the immediate error is the first which has occurred during the pre-sent cycle.
One-of-sixteen decoder 16 is illustrated in detail in Figure 3. The four binary digits comprising the destination code, which digits may be designated 2, 21, 22, and 23, are each log-ically inverted, respectively, through inverters 25, 26, 27 and 28 to provide complements o~ the input signals. The input signals, and their logical inversions, are methodically applied to the AND-gates 29-44 of an output array. Thus, by way of example, if the input destination code is 1010, only the AND-gate 39 will be enabled by virtue of the logic "1" level signals appearing di-rectly from the 23 and 21 inputs and the logic "1" level signals appearing at the outputs from the inverters ~7 and 25 which have logically inverted the 22 and 2 inputs. Thus, it will be under-stood that, for any four digit destination code input, only a single one of the output AND-gates 29-44 will be enabled.
The busy line selection logic 17 of Figure 2 may best be understood with reference to Figures 4A and 4B. Each of the outputs from the one-of-sixteen decoder 16 is coupled to one in-put each of two AND-gates in the busy line selection logic 17.
By way of example, the 1111 output from the one-of-sixteen de-coder 16 is applied to single inputs of AND-gates 53 and 69.
Busy line number 15 (BL15) is coupled through a logical inverter 88 to the remaining input of AND-gate 53 and :itself i8 directly driven by the output from AND-gate 69. The o-ther input to AND-gate 69 is connected to the Q oukput from the Request Granted flip-flop 15, Figure 2, and is thcrefore controlled by the state g _ 5~
thereof. The output ~rom the A~D-gate 53 is couple~ as one oE
the sixteen inputs to an OR-gate 78. Similarly, each of the re-maining inputs from the one-o~-sixteen decoder 16 drives one in-put each of a pair of AND-gates in the groups 45-60 and 61-76.
The output of each of the ~ND-gates 61-76 is coupled to a cor-responding one of the busy lines, and the outputs from the AND-gates 45-60 are connected directly as separate inputs to OR-gate 78. It will be noted that the output from the OR-gate 78 drives the set input of a request enable flip-flop 79. The Q output from the Request Enable flip-flop 79 is connected to one input to AND-gate 20 as shown in Figure 2.
The priority selection means is included within the bus control logic 6 as shown in Figure 1. Referring now to Figures 5~ and 5B, exemplary priority determination logic will be dis cussed. Each of the sixteen individual request lines enters the priority selection logic and i5 connected to a first input of a single one of the AND-gates 100-115. Additionally, each request input is also connected as one input to an O~-gate 116 which has its output connected to the set input of a Priority Search flip-flop 117. Thus, any priority re~uest will trigger the ~lip-flop 117 to the set state.
A four stage counter 118 has Q and Q outputs from each stage connected ko a one~of-sixteen decoder 119. The one-of-sixteen decoder 119 may have essentially the same configuration as one-of-sixteen decoder 16 shown in detail in Figure 3 with the exception that the decoder 19 also has an inverter stage disposed at each output. The output signals from one-of-sixteen decoder 119 are methodically coupled to the remaining inputs to the AND-gates 110-115 such that a single AND-gate from the array will be enabled according to the state of the four stage counter 118 and a given corresponding re~uest both being present simultaneously at the inputs to the given AND-yate.
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When the Priority Search flip~flop 117 is in the reset state, the logic "1" level observed at its Q output is applied to a reset input to the ~our stage counter 118 to rese-t all four stages o~ the counter. Since the outputs from the one-of-sixteen decoder 119 are inverted, one leg of the AND-yate 100 is enabled when the four stage counter 118 is completely reset (0000), and this status represents the highest priority which has been as-signed to the REQ 1111 signal. When the Priority Search flip-flop 117 is set by an incoming request, the logic "1" appearing at its Q output enables one input to AND-gate 120, and clock pulses appearing at its other input serve to repetitively fully enable the AND-gate 120 to correspondingly increment the four stage counter 118, thereby serving to rapidly scan the request input lines by successively partially enabling gates 100-115, one at a time. Thus, the highest priority request present will be gxanted, and a corresponding request granted signal will be issued back to the requesting local bus adapter. Any request granted signal which occurs will enable OR-gate 121, to which all outputs from the AND-gates 100-115 are also connected, and OR-gate 121 drives the reset input to priority search flip-flop 117.
When the Priority Search flip-flop 117 is reset, the "1" logic level appearing at its Q output will serve to again reset the ~our stage counter 118 in preparation for beginning a succeeding request cycle at the highest priority level.
Figure 6 illustrates a straightforward clock and timing pulse logic circuit suitable for coordinating the apparatus of Figures 1-5 in accordance with the sequential event mode selected for explaining the apparatus and its operation. The output signal from a crystal oscillator 125 is passed through a wave shaping circuit 126 which may be a Schmitt trigger or the like. The out-put signal from the wave shaping circuit 126 is thereEore a rec-tangular wave which i6 designated the clock signal. The clock '.
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signal is also applied to a frequency divider circwit 127 which may be, by way of example, four flip-flops conventionally con-nected to effect a frequen~y division of 16. The output signal from the frequency divider 127 is applied to all the clock inputs of cascaded fLip-flops 128-131. The cascaded flip-flops 128-131 may be deemed a circularly configured shift register in which a single one-bit (introduced into the first stage upon initializa-tion by means not shown) is passed from stage to stage. When each stage contains the one-bit, a "1" logic level appears at its Q output. Thus, as the circulating one-bit passes from stage to stage, pulses become successively available to coordinate events within the apparatus. These pulses are designated 01 t 02 03, and ~4.
Detailed Description of the Operation As previously noted, the operation of the exemplary ap-paratus is best understood by considering the system to operate purely sequentially. Figure 7 is an event flow diagram illus-trating the major events which take place during information transfer in accordance with the invention. Thus, Figure 7 may be referred to in conjunction with the other Figures as the de-scription of the system operation proceeds. Referring briefly again to Figure 1, let it be assumed that Subsystem A wishes to transfer a message to Subsystem F. As shown in Figure 2A, the source subsystem issues a Request signal which fully enables AND-gate 98 at 01. AND-gate 98 therefore sets the Request flip-flop 19 and, as shown in Figure 2B, also clocks the data and destina-tion code into the local bus adapter output buffer 13. It may again be noted that the subsystem's abi]ity to issue signals such as the Request signal is notoriously well known in the prior art and is not germane to the present invention.
The source local bus adapter must now determine whether the destination subsystem is availab:Le to receive the proffered . -~ .
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message. The destination code is decoded in the one-of-sixteen decoder 16 as previously described and best shown in Figure 3.
As a result, a single one of the AND-gates 29-44 is enabled, and a corresponding signal is impressed on one leg each of a pair of AND-gates in the busy line selection logic 17 as best shown in Figures 4~ and 4B. By way o~ example, it may be assumed that the destination code, which is deemed subsystem ~3's address, is 1010.
The AND-gate 39, Figure 3, in the one-of-sixteen decoder 16 will become enabled by this address, and its output signal is impressed on one input each of AND-gates 47 and 63 of the busy line selec-tion logic 17 as shown in Figure 4A. If BLll is available, i.e., not busy, it will be at the "0" logic level. This "0" logic level is inverted through the inverter 82, and a "1" logic level is therefore applied to the other input to AND-gate 47. AND-gate 47, thus fully enabled, issues a "1" logic level which is appli-ed to and enables OR-gate 78, Figure 4B. When OR-gate 78 is en-abled, its output signal drives the set input to Request Enable flip-flop 79 which is therefore forced to the set state. When the Request Enable flip-flop 79 is set, the "1" logic level appear-ing at its Q output fully enables the AND-gate 20, shown in Eigure 2A, whereby the source local bus adapter issues a request for access to the bus.
This priority request signal appears as an input to the priority search apparatus in the bus control logic as shown in Figure 5A. Assume for simplicity that the loca~ bus adapters have priority in accordance with their binary identification numbers and further assume that the requesting source local bus adapter is designated 1000. Therefore, the REQ 1000 signal will partially enable AND-gate 107 and will fully enable OR-gate 116 as shown in Eigure 5B. The output from OR-gate 116 drives the set input to Priority Search flip-flop 117 which will -therefore assume the set state. The resulting "1" logic level appearing ~0~ 5~'~
at its Q output is applied to a first input to AMD-yate 120. rrhe second input to AND-yate 120 is driven by the "clock" signal, Figure 6, such that AND-gate 120 is repetitively enabled at the clock frequency to increment the four bit counter 118, Figure 5A.
The four bit counter 118, as previously noted, starts from the count of 0000 since it would have been reset after the most re-cent previous priority search.
As the four bit counter 118 is incremented, the respec-tive first inputs to the AND-gates 100-115 driven from the one-of-sixteen decoder 119 are successively enabled. If no higher priority request is present by the time one-of-sixteen decoder 119 issues a partially enabling signal to the AND-gate 107, the AND-gate 107 will become fully enabled to honor the request by the source local bus adapter having the designation 1000. AND-gate 107 therefore issues a request granted signal back to that specific source local bus adapter. The request granted signal also enables an OR-gate 121 which drives the reset input to Priority Search flip-flop 117. When the Priority Search flip-flop 117 is reset, the AND-gate 120 is disabled such that the four stage counter 118 can no longer be incremented. Simul-taneously, the "1" logic level appearing at the Q output of the Pxiority Search flip-flop 117 is utilized to reset the four stage counter 118 back to 0000 in anticipation of a subsequent priority request cycle.
Referring again to Figure 2B, the request granted sig-nal is received by the source local bus adapter where it is ap-plied to the set input of Re~uest Granted flip-flop 15. When theRequest Granted flip-flop 15 is set, the "1" logic level ap-pearing at its Q output is applied to the control inputs to the gates in the output gate array 14 whereby the data and destina-tion information is placed onto the bus. Simultaneously, AS
best shown in Figure 4B, the "1" logic level from the Q ou-tput .
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of the Request Granted ~lip-flop is also applied to one input each of the AND-gates 61-76. Of the A~D-yates in this group, only AND-gate 63 has its other input at the "1" logic level by virtue of the lO10 signal received from one-of-sixteen decoder 16. Thus, AND-gate 63 is fully enabled to place a "1" logic level onto BLll.
Referring again to Figure 2, let it now be assumed that the local bus adapter shown is the destination. The destination local bus adapter's own busy line 97, driven to the "1" logic level by the AND-gate 63, Figure 4A, from the source local bus adapter will set the susy flip-flop 21. The resulting "l" logic level appearing at the Q output from the busy flip-~lop 21 will set the Busy Latch flip-flop 96 and will also enable the AND-gate array 23 and partially enable the AND-gate 99. When the Busy Latch flip-flop 96 assumes the set state, its Q output holds the local busy line 97 in the busy condition. Data placed on -the bus from the source local bus adapter passes through the AND-gate array 23 and is clocked into the input buffer 22 and thence to the subsystem interface 11 when the 03 signal fully enables AND-gate 99.
The information transfer is completed by carrying out routine housekeeping tasks. The subsystem performs the usual check of the received information to determine its apparent validity. For example, the subsystem will check to determine if the operation code included with the information received is the type of command to which it can respond. According to the ap-parent validity of the message received by the subsystem, a status message is issued to the status information logic 24 from the subsystem interface 11.
During the time the message is on the bus, -the bus con-trol logic checks the message parity. If the message as receiv-ed by the subsystem is apparently valid, and there is no parity Z~
error, the message transfer is deemed complete, and the ~usy flip-flop 21 and the susy Latch flip-flop 96 in the destination local bus adapter and the Request Enable flip-flop 79 and the Request Granted flip-flop 15 in the source local bus adapter are reset by ~4 in preparation for a completely new transfer within the system.
As indicated in Figure 7, if an error has occurred and it is the first error associated with the particular message transfer underway, the source local bus adapter again issues a request for the bus to the bus control and, when the request is granted, another attempt is made to carry out the message trans-fer. If the message transfer fails again on the second try, the destination local bus adapter disregards the message and turns its busy line off. No detailed apparatus is disclosed for carry-ing out these routine housekeeping tasks which are not germane to the present invention.
Thus, while the principles of the invention have now been made clear in an illustrative embodiment, there will be im-mediately obvious to those skilled in the art many modifications of structure, arrangement, proportions, elements, and components used in the practice of the invention which are particularly a-daptedfor specific environments and operating requirements with-out departing from those principles.
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means which is simple and completely reliable in oper~tion.
It is yet another object of our invention to provide such means by which the selection function is carried out ex-tremely quickly and reliably.
In a more specific aspect, it is an ob~ec-t of our in-vention to provide means by which a fundamental subsystem status, busy or not busy, is available to, and controllable by, the local bus adapters of all the other subsystems in the system.
It is a still further object of our invention to pro-vide means by which a destination subsystem can respond to actiontaken at a source local bus adapter to prepare to receive a valid message from the source subsystem.
Brief Description of the Invention Briefly, these and other objects of the invention are achieved in a data processing system apparatus for establishing a data transmission path between an originating data processor and a destination data processor. The apparatus comprises a common bus, a first local bus adapter operatively connected be-tween the originating data processor and the common bus, and a second local bus adapter operatively connected between the desti-nation data processor and the common bus. Both the first and second local bus adapters include a busy indicator means having a busy state providing an indication that the data processor coupled to said local bus adapter is busy, a means for setting the busy indicator means of the second local bus adapter to the busy state in response to a request signal from the first local bus adapter, and a means responsive to the busy state of the busy indicator means for accep-ting data from the common bus.
When one subsystem wishes to communicate wi-th another subsystem, a request is issued to the originating or source sub-system's local bus adapter along with the identi~icat.ion of the prospective destination subsystem. I'he source local bus adapter )7 ~
internally lnterrogates the busy lndicator means or busy line of the prospective destination subsystem, and if the destin3tion subsystem is not busy, the source local bus adapter issues a re-quest for access to the bus to bus control clrcuitryO If the source subsystem is the highest priority subsystem curren~ly making a request for the bus, the request is granted. In re-spo~se, the source local bus adapter sets the indicator means of the destination local bus adapter to the busy state which in-dicates to the dest~nation local bus adapter that it must prepare to receive a ~essage off the bus and also indicates to all other prospectiv~ source subsystems tha~ the selected destinatlon sub-system is temporarily unavailable to themO After the message is transmitted, both the source and destin~tion local bus adapters enter a status cycle to check the lntegrity of the transmitted messageO Thereafter, the destination subsystem resets its own indicator means and once again beco~es available ~o accept a subsequent me~sage from any local bu~ adapter which m2y be able to set its indieator means.
The subject matter of the ~nvent~on is particularly pointed out and distinctly claimed in the concluding por~ion of the speclficationO The invention, however, both as to organiza~
tion and method of operation, may best be understood by reference to the following description ~aken in connection with the sub-joined claims and the accompanylng drawings of which:
Figure 1 is a major block diagram of a bus oriented data processing system comprisi~g an exemplary environment in which our invention ~inds use;
Figures ~A and 2B, taken to~ether, are a logic block diagram of a local bus adapter module from the system of Flgure l;
Figure 3 is a detailed logic cliagr~m of a one~of-~lx~
~een decoder repre~e~ted a~ a logic block ln Flgure 2;
Figures 4A and 4B, taken together, are a detailed ~ .. .. .
~ 4 -~ ~ ~ 7 ~ S ~ ~
logic diagram of busy line selection logic represen~ed ~s a loglc block ln Flgure 2, Figures 5A and 5B 7 ta~en together, are a logic diagram of priority determination selection logic which is contained within the bus control major logic block of Figure l;
Figure 6 illustrates simple clock and timlng pulse derivation logic by which the sign~ls necessary to coordinate the orderly sequential operation of the system are obtained; and Figure 7 is a~ event sequence flow diagram which illus-trates the operation and ~nteraction of the various sy~tem con~stituents by which information ~ransfer is ~arried out according to our invent ion O
Detailed Description of the Apparatus The logic diagrams are present~d ln slightly simpli-fied form in order that the inventive roncept may be more readily understood. For example, instan~aneous response tlm2s are as-sumed such that no specia 1 circuitry is shown for overcoming logic race conditions which may occur as the speed of operation is increased until the circuits cannot be assumed ~o respond ~m-mediately~ The changes and additions required to overcome loglcrace conditions and other problems associated with extremely high speed operation are known to all skilled in the art and are of no consequence to an understandlng of the invention. To fur-ther clarify the inventive concepts, the logic is presented using the most basic types of AND-gates, OR-gates, flip-flops, etc. It ~s apparent that the inventive concepts can be realized and practiced utilizing the more complex types of logic elements which are now generally incorpora~ed into contemporary data pro-cessing sys~ems becau~e of the availabillty and general use of integrated circuits directly reallzing such complex logic ele-ments. Further, the operation of the apparatus ls presented in sz~
a strictly sequential form. Of cour9e, co~vent~onal t-lming practice in data processing appara~us u~illzes, to the ~ullest extent possible, overlapping and simultaneous logic operations to increase overall speed. I~ is believed that the invention would be obscured by the inclusion of all the logic in its most complex form of the exact machine embodiment in which the inven-tion is currently practiced.
A~tention is now directPd ~o Figure 1 which illustrates, in a block diagram, an exemplary data processing system in which the pre~ent invention flnds use. The data processing system of Figure 1 is bus oriented in that all the subsystems, including the processor subsystem 1, are coupled to one another by means of an internal transfer bus 2. The internal transfer bus is incor-poxated into an internal transfer bus subsystem 3 which also in-cludes a plurallty of local bus adapters 4, an interbus communi-cation adapter 5, bus control loglc 6, and timing logic 7. In the internal transfer subsystem to be described, up to 16 local bus adapters and interbus communicatlon adapters may be coupled to the internal transfer bus 2. Typically, only one interbus communication adapter 5 is provided. Undesignated subsystems 8 may constitute any of the subsystems or data processors usually found in a bus-orLented data processing system;~
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e.g.: core memory, tape units, disk units, printers, video dis-plays, etc. The service subsystem 9 may include a system console to effect two-way communication between an operator an~ the data processing system.
The function of the internal transfer bus 2 is to trans-mit information from one local bus adapter to another local bus adapter. It defines the paths and procedures to be used by the local bus adapters to communicate with each other. All informa-tion is passed over the internal transEer bus sequentially fol-lowing the common procedure defined by the internal transfer busprotocol. The identical local bus adapters 4 interface every subsystem to the internal transfer bus. Each local bus adapter performs all the logic operations necessary to insure that the internal transfer bus discipline is maintained at all times.
The bus control logic 6 performs several functions. Of most direct interest to the present invention, it arbitrates all local bus adapter reques-ts to use the internal transfer bus.
This is accomplished on a fixed priority basis in the exemplary embodiment. Each local bus adapter is assigned a specific pri-ority, and in case of simultaneous requests, the bus control honors the local bus adapter having the highest priority. The bus control logic also checks the parity of all messages sent over the internal transfer bus and reflects the result of the parity check onto the internal transfer bus for analysis by the communicating local bus adapters. The bus control logic can com-municate with the service subsystems 9 and the processor sub-system 1 by means of the serial service bus 10 in order to pro-vide certain system condition history and status information and signals of no direct consequence to the present invention.
The internal transfer subsystem is a synchronous logic machine in that all operations in the internal transfer subsystem are synchronized with clock and phase signals emanating from the ~;371~S~
~iming logic 7.
Referring now to Figures 2A and 2B, the apparatus com-prising an exemplary local bus adapter will be discllssed. The local bus adapter is disposed between a subsystem interface 11 and an internal transfer bus interface 12. The local bus adapter receives request, data~ destinatlon, and status information from its associated subsystem at the interface 11. Those skilled in the art will appreciate that such information is routinely avail-able from typical subsystems used in bus oriented data processing systems. The local bus adapter receives data, opcode, busy line, request-granted, and parity error information from the bus inter-face 12. The data and opcode information is selectively passed on to the subsystem. Similarly, the data and destination infor-mation received from the subsystem is selectively issued to the bus interface 12. In addition, the local bus adapter can issue a Request signal to the bus and also can affect the status of any one of the busy lines brought into the local bus adapter.
Data and destination information from the subsystem interface 11 is applied to an output buffer 13 and clocked into the buffer when the Subsystem Request flip-flop 19 is set. This same data and destination information is taken from the ou-tput buffer and applied to an output AND-gate array 14. Transfer of this information through the output AND-gate array 14 is control-led by the state of a Request Granted flip-flop 15 which has its ~ output connected to each of the gates in the array. The desti-nation code from the output buffer 13, which in the exemplary em-bodiment constitutes a 4 bit code designating ports 0000 through 1111 (i.e., 0 through 15), is applied to a one-of-sixteen decoder 16. One-of-sixteen decoder 16, which is described in detail be-low, issue~s an enabling signal ~rom a single one of its sixteenoutputs according to the binary configuration oE the input desti-nation code. The sixteen output lines from one-of-sixteen decoder 16 are applied to busy line selection logic 17 which also receives an input from the Q output of the Request Granted flip-flop 15. The busy lines 18 of all the subsystems in the system are also available for monitoring by the busy line selection logic 17. The busy line selection logic 17, which will be de-scribed in detail below, also includes means for selectively forcing any one of the busy lines 18 to the busy state.
A Request signal received from the subsystem interface 11 passes through a time controlled AND-gate 98 and is used to set the Request flip-flop 19. The Q output from the Request flip-flop 19 is applied as one input to an AND-gate 20, and, as previously noted, to the in-clock input to the output buffer 13.
The other input to the AND-gate 20, which serves to issue a priority request signal from the local bus adapter to the bus interface 12, is received from the busy line selection logic 17.
Information received from the bus interface 12 is gated to an input buffer 22 through an input AND-gate array 23 when a Busy flip-flop 21 is in the set state because the Q output there-from is coupled to enable the gates in the array 23. The ~ out-put from the Busy flip-flop is also applied to the set input of a Busy Line Latch flip-flop 96, and the Q output from the Busy Line Latch flip-flop is connected to the immediate local bus adapter's own busy line 97. Thus, once set, the Busy Line Latch flip-flop 96 holds the corresponding busy line in the busy state until the Busy Line Latch flip-flop is subsequently reset. The manner in which another local bus adapter raises the busy line 97 to set the Busy flip-flop 21 will be discussed below.
At the end of a message transmission cycle, a status check is carried out to determine the val:idity oE the received message. If the message is unacceptable to the receiving sub-system (such as including the opcode of a command which the particular subsystem is incapable of executing), the subsystem provides a corresponding signal to the status logic 24. Similar-ly, if a parity error i5 detected by the bus control logic 6 (Figure 1) a parity error signal is applied to the status logic 24. Thus, either type of error will be sensed by the status logic which also has the facility for determining whether the immediate error is the first which has occurred during the pre-sent cycle.
One-of-sixteen decoder 16 is illustrated in detail in Figure 3. The four binary digits comprising the destination code, which digits may be designated 2, 21, 22, and 23, are each log-ically inverted, respectively, through inverters 25, 26, 27 and 28 to provide complements o~ the input signals. The input signals, and their logical inversions, are methodically applied to the AND-gates 29-44 of an output array. Thus, by way of example, if the input destination code is 1010, only the AND-gate 39 will be enabled by virtue of the logic "1" level signals appearing di-rectly from the 23 and 21 inputs and the logic "1" level signals appearing at the outputs from the inverters ~7 and 25 which have logically inverted the 22 and 2 inputs. Thus, it will be under-stood that, for any four digit destination code input, only a single one of the output AND-gates 29-44 will be enabled.
The busy line selection logic 17 of Figure 2 may best be understood with reference to Figures 4A and 4B. Each of the outputs from the one-of-sixteen decoder 16 is coupled to one in-put each of two AND-gates in the busy line selection logic 17.
By way of example, the 1111 output from the one-of-sixteen de-coder 16 is applied to single inputs of AND-gates 53 and 69.
Busy line number 15 (BL15) is coupled through a logical inverter 88 to the remaining input of AND-gate 53 and :itself i8 directly driven by the output from AND-gate 69. The o-ther input to AND-gate 69 is connected to the Q oukput from the Request Granted flip-flop 15, Figure 2, and is thcrefore controlled by the state g _ 5~
thereof. The output ~rom the A~D-gate 53 is couple~ as one oE
the sixteen inputs to an OR-gate 78. Similarly, each of the re-maining inputs from the one-o~-sixteen decoder 16 drives one in-put each of a pair of AND-gates in the groups 45-60 and 61-76.
The output of each of the ~ND-gates 61-76 is coupled to a cor-responding one of the busy lines, and the outputs from the AND-gates 45-60 are connected directly as separate inputs to OR-gate 78. It will be noted that the output from the OR-gate 78 drives the set input of a request enable flip-flop 79. The Q output from the Request Enable flip-flop 79 is connected to one input to AND-gate 20 as shown in Figure 2.
The priority selection means is included within the bus control logic 6 as shown in Figure 1. Referring now to Figures 5~ and 5B, exemplary priority determination logic will be dis cussed. Each of the sixteen individual request lines enters the priority selection logic and i5 connected to a first input of a single one of the AND-gates 100-115. Additionally, each request input is also connected as one input to an O~-gate 116 which has its output connected to the set input of a Priority Search flip-flop 117. Thus, any priority re~uest will trigger the ~lip-flop 117 to the set state.
A four stage counter 118 has Q and Q outputs from each stage connected ko a one~of-sixteen decoder 119. The one-of-sixteen decoder 119 may have essentially the same configuration as one-of-sixteen decoder 16 shown in detail in Figure 3 with the exception that the decoder 19 also has an inverter stage disposed at each output. The output signals from one-of-sixteen decoder 119 are methodically coupled to the remaining inputs to the AND-gates 110-115 such that a single AND-gate from the array will be enabled according to the state of the four stage counter 118 and a given corresponding re~uest both being present simultaneously at the inputs to the given AND-yate.
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When the Priority Search flip~flop 117 is in the reset state, the logic "1" level observed at its Q output is applied to a reset input to the ~our stage counter 118 to rese-t all four stages o~ the counter. Since the outputs from the one-of-sixteen decoder 119 are inverted, one leg of the AND-yate 100 is enabled when the four stage counter 118 is completely reset (0000), and this status represents the highest priority which has been as-signed to the REQ 1111 signal. When the Priority Search flip-flop 117 is set by an incoming request, the logic "1" appearing at its Q output enables one input to AND-gate 120, and clock pulses appearing at its other input serve to repetitively fully enable the AND-gate 120 to correspondingly increment the four stage counter 118, thereby serving to rapidly scan the request input lines by successively partially enabling gates 100-115, one at a time. Thus, the highest priority request present will be gxanted, and a corresponding request granted signal will be issued back to the requesting local bus adapter. Any request granted signal which occurs will enable OR-gate 121, to which all outputs from the AND-gates 100-115 are also connected, and OR-gate 121 drives the reset input to priority search flip-flop 117.
When the Priority Search flip-flop 117 is reset, the "1" logic level appearing at its Q output will serve to again reset the ~our stage counter 118 in preparation for beginning a succeeding request cycle at the highest priority level.
Figure 6 illustrates a straightforward clock and timing pulse logic circuit suitable for coordinating the apparatus of Figures 1-5 in accordance with the sequential event mode selected for explaining the apparatus and its operation. The output signal from a crystal oscillator 125 is passed through a wave shaping circuit 126 which may be a Schmitt trigger or the like. The out-put signal from the wave shaping circuit 126 is thereEore a rec-tangular wave which i6 designated the clock signal. The clock '.
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signal is also applied to a frequency divider circwit 127 which may be, by way of example, four flip-flops conventionally con-nected to effect a frequen~y division of 16. The output signal from the frequency divider 127 is applied to all the clock inputs of cascaded fLip-flops 128-131. The cascaded flip-flops 128-131 may be deemed a circularly configured shift register in which a single one-bit (introduced into the first stage upon initializa-tion by means not shown) is passed from stage to stage. When each stage contains the one-bit, a "1" logic level appears at its Q output. Thus, as the circulating one-bit passes from stage to stage, pulses become successively available to coordinate events within the apparatus. These pulses are designated 01 t 02 03, and ~4.
Detailed Description of the Operation As previously noted, the operation of the exemplary ap-paratus is best understood by considering the system to operate purely sequentially. Figure 7 is an event flow diagram illus-trating the major events which take place during information transfer in accordance with the invention. Thus, Figure 7 may be referred to in conjunction with the other Figures as the de-scription of the system operation proceeds. Referring briefly again to Figure 1, let it be assumed that Subsystem A wishes to transfer a message to Subsystem F. As shown in Figure 2A, the source subsystem issues a Request signal which fully enables AND-gate 98 at 01. AND-gate 98 therefore sets the Request flip-flop 19 and, as shown in Figure 2B, also clocks the data and destina-tion code into the local bus adapter output buffer 13. It may again be noted that the subsystem's abi]ity to issue signals such as the Request signal is notoriously well known in the prior art and is not germane to the present invention.
The source local bus adapter must now determine whether the destination subsystem is availab:Le to receive the proffered . -~ .
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message. The destination code is decoded in the one-of-sixteen decoder 16 as previously described and best shown in Figure 3.
As a result, a single one of the AND-gates 29-44 is enabled, and a corresponding signal is impressed on one leg each of a pair of AND-gates in the busy line selection logic 17 as best shown in Figures 4~ and 4B. By way o~ example, it may be assumed that the destination code, which is deemed subsystem ~3's address, is 1010.
The AND-gate 39, Figure 3, in the one-of-sixteen decoder 16 will become enabled by this address, and its output signal is impressed on one input each of AND-gates 47 and 63 of the busy line selec-tion logic 17 as shown in Figure 4A. If BLll is available, i.e., not busy, it will be at the "0" logic level. This "0" logic level is inverted through the inverter 82, and a "1" logic level is therefore applied to the other input to AND-gate 47. AND-gate 47, thus fully enabled, issues a "1" logic level which is appli-ed to and enables OR-gate 78, Figure 4B. When OR-gate 78 is en-abled, its output signal drives the set input to Request Enable flip-flop 79 which is therefore forced to the set state. When the Request Enable flip-flop 79 is set, the "1" logic level appear-ing at its Q output fully enables the AND-gate 20, shown in Eigure 2A, whereby the source local bus adapter issues a request for access to the bus.
This priority request signal appears as an input to the priority search apparatus in the bus control logic as shown in Figure 5A. Assume for simplicity that the loca~ bus adapters have priority in accordance with their binary identification numbers and further assume that the requesting source local bus adapter is designated 1000. Therefore, the REQ 1000 signal will partially enable AND-gate 107 and will fully enable OR-gate 116 as shown in Eigure 5B. The output from OR-gate 116 drives the set input to Priority Search flip-flop 117 which will -therefore assume the set state. The resulting "1" logic level appearing ~0~ 5~'~
at its Q output is applied to a first input to AMD-yate 120. rrhe second input to AND-yate 120 is driven by the "clock" signal, Figure 6, such that AND-gate 120 is repetitively enabled at the clock frequency to increment the four bit counter 118, Figure 5A.
The four bit counter 118, as previously noted, starts from the count of 0000 since it would have been reset after the most re-cent previous priority search.
As the four bit counter 118 is incremented, the respec-tive first inputs to the AND-gates 100-115 driven from the one-of-sixteen decoder 119 are successively enabled. If no higher priority request is present by the time one-of-sixteen decoder 119 issues a partially enabling signal to the AND-gate 107, the AND-gate 107 will become fully enabled to honor the request by the source local bus adapter having the designation 1000. AND-gate 107 therefore issues a request granted signal back to that specific source local bus adapter. The request granted signal also enables an OR-gate 121 which drives the reset input to Priority Search flip-flop 117. When the Priority Search flip-flop 117 is reset, the AND-gate 120 is disabled such that the four stage counter 118 can no longer be incremented. Simul-taneously, the "1" logic level appearing at the Q output of the Pxiority Search flip-flop 117 is utilized to reset the four stage counter 118 back to 0000 in anticipation of a subsequent priority request cycle.
Referring again to Figure 2B, the request granted sig-nal is received by the source local bus adapter where it is ap-plied to the set input of Re~uest Granted flip-flop 15. When theRequest Granted flip-flop 15 is set, the "1" logic level ap-pearing at its Q output is applied to the control inputs to the gates in the output gate array 14 whereby the data and destina-tion information is placed onto the bus. Simultaneously, AS
best shown in Figure 4B, the "1" logic level from the Q ou-tput .
., ~07~
of the Request Granted ~lip-flop is also applied to one input each of the AND-gates 61-76. Of the A~D-yates in this group, only AND-gate 63 has its other input at the "1" logic level by virtue of the lO10 signal received from one-of-sixteen decoder 16. Thus, AND-gate 63 is fully enabled to place a "1" logic level onto BLll.
Referring again to Figure 2, let it now be assumed that the local bus adapter shown is the destination. The destination local bus adapter's own busy line 97, driven to the "1" logic level by the AND-gate 63, Figure 4A, from the source local bus adapter will set the susy flip-flop 21. The resulting "l" logic level appearing at the Q output from the busy flip-~lop 21 will set the Busy Latch flip-flop 96 and will also enable the AND-gate array 23 and partially enable the AND-gate 99. When the Busy Latch flip-flop 96 assumes the set state, its Q output holds the local busy line 97 in the busy condition. Data placed on -the bus from the source local bus adapter passes through the AND-gate array 23 and is clocked into the input buffer 22 and thence to the subsystem interface 11 when the 03 signal fully enables AND-gate 99.
The information transfer is completed by carrying out routine housekeeping tasks. The subsystem performs the usual check of the received information to determine its apparent validity. For example, the subsystem will check to determine if the operation code included with the information received is the type of command to which it can respond. According to the ap-parent validity of the message received by the subsystem, a status message is issued to the status information logic 24 from the subsystem interface 11.
During the time the message is on the bus, -the bus con-trol logic checks the message parity. If the message as receiv-ed by the subsystem is apparently valid, and there is no parity Z~
error, the message transfer is deemed complete, and the ~usy flip-flop 21 and the susy Latch flip-flop 96 in the destination local bus adapter and the Request Enable flip-flop 79 and the Request Granted flip-flop 15 in the source local bus adapter are reset by ~4 in preparation for a completely new transfer within the system.
As indicated in Figure 7, if an error has occurred and it is the first error associated with the particular message transfer underway, the source local bus adapter again issues a request for the bus to the bus control and, when the request is granted, another attempt is made to carry out the message trans-fer. If the message transfer fails again on the second try, the destination local bus adapter disregards the message and turns its busy line off. No detailed apparatus is disclosed for carry-ing out these routine housekeeping tasks which are not germane to the present invention.
Thus, while the principles of the invention have now been made clear in an illustrative embodiment, there will be im-mediately obvious to those skilled in the art many modifications of structure, arrangement, proportions, elements, and components used in the practice of the invention which are particularly a-daptedfor specific environments and operating requirements with-out departing from those principles.
Claims (8)
1. In a data processing system which includes a plurality of data processors adapted to communicate with one another, each such data processor including means for issuing a request signal, a destination signal, and data to be transferred to another data processor, apparatus for establishing a data transmission path, between an originating data processor and a destination data pro-cessor comprising: a. a common bus; b. a plurality of local bus adapters corresponding in number to said plurality of data processors, each local bus adapter operatively connected between a respective one of the data processors and the said common bus, each of said local bus adapters including: 1. busy indicator means having first and second states, said first state providing an indication that a data processor coupled to the local bus adapter is busy; 2. means for individually setting its own said busy indicator means and any one of the other of said local bus adapters coupled to said common bus to said first state; and 3.
means responsive to said first state of the indicator means in-cluded therewith for accepting data from said common bus.
means responsive to said first state of the indicator means in-cluded therewith for accepting data from said common bus.
2. A data processing system in accordance with claim 1 and which further includes priority selection means for arbitrating simultaneous or nearly simultaneous requests by originating local bus adapters for use of said common bus by issuing a granted bus request signal only to the selected local bus adapter, each of said local bus adapters further including: a. means responsive to the reception of a request signal and a destination code from the originating data processor and to a sensed second state of said busy indicator means in the designated destinaition local bus adapter, which second state indicates that the data processor operatively connected to said destination local bus adapter is 2 (concluded) not in the busy state, for issuing a request for access to said common bus to the priority selection means; and b. means re-sponsive to a granted bus request signal for transferring data to said common bus.
3. A data processing system in accordance with claim 2 which each of said local bus adapters further includes means responsive to said second state of said busy indicator means in-cluded therewith for transferring data from said common bus to the data processor connected to said local bus adapter.
4. The data processing system of claim 3 in which said busy indicator means comprises a first bistable logic element having a set input and an output providing a logic level indica-tion of the state thereof.
5. The data processing system of claim 4 in which said busy indicator means further includes: A. a second bistable logic element having a set input and an output providing a logic level indication of the state thereof; B. means coupling said output at said first bistable logic element to said set input of said second bistable logic element; C. a busy line; D. means coupling said busy line to said set input of said first bistable logic element; and E. means coupling said busy line to said out-put of said second bistable logic element.
6. The data processing system of claim 5 in which each local bus adapter further includes: A. decoder means adapted to receive the destination code from the data processor coupled to said local bus adapter and to issue a unique signal identifying a prospective destination local bus adapter in accordance with the destination code; and B. busy line select logic responsive to the combination of: 1. said unique signal; 2, a sensed second 6 (concluded) state of said busy indicator means in the one of said local bus adapters identified by said unique signal; and 3. a granted bus request signal; for applying a set signal to the busy line of the one of said local bus adapters identified by said unique signal whereby said first bistable logic element in the said one local bus adapter identified by said unique signal is set to said first state.
7. The data processing system of claim 6 in which said busy line select logic includes means for logically combining said unique signal and the logic level appearing on the one said busy line of the one said local bus adapter identified by said unique signal when said first bistable logic element therein is in said first state and for issuing a request signal to the priority selection means when the logical combination is true.
8. In a data processing system apparatus for establishing a data transmission path between an originating data processor and a destination data processor comprising: A. a common bus;
B. a first local bus adapter operatively connected between the originating data processor and said common bus; C. a second local bus adapter operatively connected between the destination data processor and said common bus; D. each of said first and second local bus adapters including: 1. busy indicator means having a busy state providing an indication that the data proces-sor coupled to said local bus adapter is busy; 2. means for set-ting said busy indicator means of said second local bus adapter to said busy state in response to a request signal from said first local bus adapter; and 3. means responsive to said busy state of said busy indicator means for accepting data from said common bus.
B. a first local bus adapter operatively connected between the originating data processor and said common bus; C. a second local bus adapter operatively connected between the destination data processor and said common bus; D. each of said first and second local bus adapters including: 1. busy indicator means having a busy state providing an indication that the data proces-sor coupled to said local bus adapter is busy; 2. means for set-ting said busy indicator means of said second local bus adapter to said busy state in response to a request signal from said first local bus adapter; and 3. means responsive to said busy state of said busy indicator means for accepting data from said common bus.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/633,345 US4038644A (en) | 1975-11-19 | 1975-11-19 | Destination selection apparatus for a bus oriented computer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1078524A true CA1078524A (en) | 1980-05-27 |
Family
ID=24539271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA263,608A Expired CA1078524A (en) | 1975-11-19 | 1976-10-18 | Destination selection apparatus for a bus oriented computer system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4038644A (en) |
| JP (1) | JPS5936772B2 (en) |
| CA (1) | CA1078524A (en) |
| DE (1) | DE2652303C2 (en) |
| FR (1) | FR2332572A1 (en) |
| GB (1) | GB1518565A (en) |
Families Citing this family (69)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4161025A (en) * | 1973-12-04 | 1979-07-10 | Compagnie Internationale Pour L'informatique | Information processing system |
| US4181938A (en) * | 1975-10-15 | 1980-01-01 | Tokyo Shibaura Electric Co., Ltd. | Processor device |
| US4228496A (en) * | 1976-09-07 | 1980-10-14 | Tandem Computers Incorporated | Multiprocessor system |
| US4213176A (en) * | 1976-12-22 | 1980-07-15 | Ncr Corporation | System and method for increasing the output data throughput of a computer |
| JPS5427746A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Bus control system of composite computer system |
| JPS5427737A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Bus control system |
| JPS5427739A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Information processing system |
| JPS5427735A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Information processing organization |
| JPS5427748A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Bus control system of composite computer system |
| JPS5427736A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Bus control system |
| JPS5427740A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Information processing unit |
| JPS5427742A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Data transfer system |
| JPS5427743A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Information processing unit |
| JPS5427747A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Interruption system of composite computer system |
| JPS5427741A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Information processing organization |
| JPS5427745A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Addressing system of composite computer system |
| JPS5427738A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Bus stall processing system |
| JPS581449B2 (en) * | 1977-08-03 | 1983-01-11 | 株式会社東芝 | computer complex system |
| US4161786A (en) * | 1978-02-27 | 1979-07-17 | The Mitre Corporation | Digital bus communications system |
| US4361876A (en) * | 1978-09-05 | 1982-11-30 | Motorola, Inc. | Microcomputer with logic for selectively disabling serial communications |
| US4236209A (en) * | 1978-10-31 | 1980-11-25 | Honeywell Information Systems Inc. | Intersystem transaction identification logic |
| US4234919A (en) * | 1978-10-31 | 1980-11-18 | Honeywell Information Systems Inc. | Intersystem communication link |
| IT1100916B (en) * | 1978-11-06 | 1985-09-28 | Honeywell Inf Systems | APPARATUS FOR MANAGEMENT OF DATA TRANSFER REQUESTS IN DATA PROCESSING SYSTEMS |
| US4281380A (en) * | 1978-12-27 | 1981-07-28 | Harris Corporation | Bus collision avoidance system for distributed network data processing communications system |
| US4263649A (en) * | 1979-01-05 | 1981-04-21 | Mohawk Data Sciences Corp. | Computer system with two busses |
| US4300194A (en) * | 1979-01-31 | 1981-11-10 | Honeywell Information Systems Inc. | Data processing system having multiple common buses |
| US4292623A (en) * | 1979-06-29 | 1981-09-29 | International Business Machines Corporation | Port logic for a communication bus system |
| US4649470A (en) * | 1980-02-11 | 1987-03-10 | Data General Corporation | Data processing system |
| US4419724A (en) * | 1980-04-14 | 1983-12-06 | Sperry Corporation | Main bus interface package |
| US4325147A (en) * | 1980-06-16 | 1982-04-13 | Minnesota Mining & Manufacturing Co. | Asynchronous multiplex system |
| GB2214334B (en) * | 1988-01-05 | 1992-05-06 | Texas Instruments Ltd | Integrated circuit |
| US4375639A (en) * | 1981-01-12 | 1983-03-01 | Harris Corporation | Synchronous bus arbiter |
| DE3107871C2 (en) * | 1981-03-02 | 1982-11-18 | Computer Gesellschaft Konstanz Mbh, 7750 Konstanz | Method and circuit arrangement for controlling the data transport between individual functional units of a data processing system |
| US4493021A (en) * | 1981-04-03 | 1985-01-08 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Multicomputer communication system |
| JPS58501557A (en) * | 1981-09-29 | 1983-09-16 | バロース コーポレーション | How to drive a bus in a data processing system |
| EP0075625B1 (en) * | 1981-09-29 | 1986-12-10 | BURROUGHS CORPORATION (a Delaware corporation) | Conversation bus for a data processing system |
| GB2117939A (en) * | 1982-03-29 | 1983-10-19 | Ncr Co | Data communication network and method of communication |
| US4639860A (en) * | 1982-05-12 | 1987-01-27 | Honeywell Information Systems Inc. | Wrap-around logic for interprocessor communications |
| US4563774A (en) * | 1982-10-25 | 1986-01-07 | At&T Bell Laboratories | Address coded communication system |
| DE3407870C1 (en) * | 1984-03-02 | 1985-08-14 | Nixdorf Computer Ag, 4790 Paderborn | Method and circuit arrangement for initiating a data transmission connection |
| US4639859A (en) * | 1984-05-24 | 1987-01-27 | Rca Corporation | Priority arbitration logic for a multi-master bus system |
| GB2162406B (en) * | 1984-06-18 | 1988-03-09 | Logica | Computer system |
| US4768145A (en) * | 1984-11-28 | 1988-08-30 | Hewlett-Packard Company | Bus system |
| DD248615B1 (en) * | 1984-12-27 | 1990-10-10 | Textima Veb K | DEVICE AND METHOD FOR CONTROLLING KNITTING MACHINES |
| DE3500254C2 (en) * | 1985-01-05 | 1997-01-09 | Intel Corp | High speed parallel bus structure and method for data transmission |
| JP2548693B2 (en) * | 1985-03-13 | 1996-10-30 | キヤノン株式会社 | Serial data communication system and device |
| IT1184553B (en) * | 1985-05-07 | 1987-10-28 | Honeywell Inf Systems | SYSTEM ARCHITECTURE WITH MULTIPLE PROCESSORS |
| US4912627A (en) * | 1985-08-14 | 1990-03-27 | Apple Computer, Inc. | Method for storing a second number as a command address of a first peripheral device and a third number as a command address of a second peripheral device |
| US4910655A (en) * | 1985-08-14 | 1990-03-20 | Apple Computer, Inc. | Apparatus for transferring signals and data under the control of a host computer |
| US4875158A (en) * | 1985-08-14 | 1989-10-17 | Apple Computer, Inc. | Method for requesting service by a device which generates a service request signal successively until it is serviced |
| US4918598A (en) * | 1985-08-14 | 1990-04-17 | Apple Computer, Inc. | Method for selectively activating and deactivating devices having same first address and different extended addresses |
| US4796176A (en) | 1985-11-15 | 1989-01-03 | Data General Corporation | Interrupt handling in a multiprocessor computing system |
| JPH032236Y2 (en) * | 1985-12-27 | 1991-01-22 | ||
| US4785394A (en) * | 1986-09-19 | 1988-11-15 | Datapoint Corporation | Fair arbitration technique for a split transaction bus in a multiprocessor computer system |
| FR2605767B1 (en) * | 1986-10-22 | 1989-04-28 | Olivier Alain | METHOD FOR HOLDING AT LEAST ONE INFORMATION PROCESSING EQUIPMENT THEN BINDING SAME TO EQUIPMENT AND MEANS FOR CARRYING OUT THIS METHOD |
| CA1283962C (en) * | 1986-12-08 | 1991-05-07 | Gerald F. Youngblood | Apparatus and method for communication between host cpu and remote terminal |
| US4835673A (en) * | 1987-04-27 | 1989-05-30 | Ncr Corporation | Method and apparatus for sharing resources among multiple processing systems |
| US5029074A (en) * | 1987-06-29 | 1991-07-02 | Digital Equipment Corporation | Bus adapter unit for digital processing system |
| JPS6449196U (en) * | 1987-09-21 | 1989-03-27 | ||
| JPH0786853B2 (en) * | 1988-02-29 | 1995-09-20 | 株式会社ピーエフユー | Bus transfer control method |
| IT1227711B (en) * | 1988-11-18 | 1991-05-06 | Caluso Torino | MULTIPROCESSOR SYSTEM FOR DATA PROCESSING TO SHARED DISTRIBUTED RESOURCES AND STALL PREVENTION. |
| US5414818A (en) * | 1990-04-06 | 1995-05-09 | Mti Technology Corporation | Method and apparatus for controlling reselection of a bus by overriding a prioritization protocol |
| ATE137038T1 (en) * | 1990-08-31 | 1996-05-15 | Advanced Micro Devices Inc | TRANSMISSION CONTROL SYSTEM FOR A COMPUTER AND PERIPHERAL DEVICES |
| WO1995020191A1 (en) * | 1994-01-25 | 1995-07-27 | Apple Computer, Inc. | System and method for coordinating access to a bus |
| WO1995020193A1 (en) * | 1994-01-25 | 1995-07-27 | Apple Computer, Inc. | Improved bus protocol using separate clocks for arbitration and data transfer |
| US5657455A (en) * | 1994-09-07 | 1997-08-12 | Adaptec, Inc. | Status indicator for a host adapter |
| US6081860A (en) * | 1997-11-20 | 2000-06-27 | International Business Machines Corporation | Address pipelining for data transfers |
| US7054969B1 (en) * | 1998-09-18 | 2006-05-30 | Clearspeed Technology Plc | Apparatus for use in a computer system |
| US7194663B2 (en) * | 2003-11-18 | 2007-03-20 | Honeywell International, Inc. | Protective bus interface and method |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3242467A (en) * | 1960-06-07 | 1966-03-22 | Ibm | Temporary storage register |
| US3253262A (en) * | 1960-12-30 | 1966-05-24 | Bunker Ramo | Data processing system |
| US3286240A (en) * | 1962-12-31 | 1966-11-15 | Ibm | Channel status checking and switching system |
| US3323109A (en) * | 1963-12-30 | 1967-05-30 | North American Aviation Inc | Multiple computer-multiple memory system |
| US3470542A (en) * | 1967-03-17 | 1969-09-30 | Wang Laboratories | Modular system design |
| US3445822A (en) * | 1967-07-14 | 1969-05-20 | Ibm | Communication arrangement in data processing system |
| US3710324A (en) * | 1970-04-01 | 1973-01-09 | Digital Equipment Corp | Data processing system |
| FR2212963A5 (en) * | 1972-12-28 | 1974-07-26 | Cit Alcatel | |
| US3940743A (en) * | 1973-11-05 | 1976-02-24 | Digital Equipment Corporation | Interconnecting unit for independently operable data processing systems |
-
1975
- 1975-11-19 US US05/633,345 patent/US4038644A/en not_active Expired - Lifetime
-
1976
- 1976-10-18 CA CA263,608A patent/CA1078524A/en not_active Expired
- 1976-11-04 GB GB45915/76A patent/GB1518565A/en not_active Expired
- 1976-11-16 JP JP51136952A patent/JPS5936772B2/en not_active Expired
- 1976-11-17 DE DE2652303A patent/DE2652303C2/en not_active Expired
- 1976-11-18 FR FR7634708A patent/FR2332572A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE2652303A1 (en) | 1977-05-26 |
| GB1518565A (en) | 1978-07-19 |
| JPS5263638A (en) | 1977-05-26 |
| DE2652303C2 (en) | 1981-10-08 |
| US4038644A (en) | 1977-07-26 |
| FR2332572A1 (en) | 1977-06-17 |
| FR2332572B1 (en) | 1980-04-30 |
| JPS5936772B2 (en) | 1984-09-05 |
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Legal Events
| Date | Code | Title | Description |
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| MKEX | Expiry |