CA1074016A - Data expansion apparatus - Google Patents
Data expansion apparatusInfo
- Publication number
- CA1074016A CA1074016A CA280,453A CA280453A CA1074016A CA 1074016 A CA1074016 A CA 1074016A CA 280453 A CA280453 A CA 280453A CA 1074016 A CA1074016 A CA 1074016A
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- Canada
- Prior art keywords
- data
- register
- storage
- length
- segment
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/46—Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
- G09G1/02—Storage circuits
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/42—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Remote Sensing (AREA)
- Radar, Positioning & Navigation (AREA)
- Digital Computer Display Output (AREA)
- Memory System (AREA)
- Executing Machine-Instructions (AREA)
- Debugging And Monitoring (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Image Generation (AREA)
Abstract
DATA EXPANSION APPARATUS
Abstract of The Disclosure When a data stream includes long sections of data that are repeated periodically, storage space may be saved by not including full repetitions of such sections in the storage. However, when the data is to be read from storage for utilization, the omitted repetitious sections must be inserted. This is accomplished by providing hardware apparatus which recognizes a particular flag occurring in the stored data. After recognizing the flag, the expansion apparatus interprets the next piece of information in the data stream as being the storage address of the start of a section of data that is to be inserted into the data stream; the next piece of information is interpreted as being the length of the section of data to be inserted; and the next following piece of information is the number of times that the section of data is to be inserted. The apparatus will respond to the flag and its associated indicators by inserting the appropriate data section the indicated number of times.
Abstract of The Disclosure When a data stream includes long sections of data that are repeated periodically, storage space may be saved by not including full repetitions of such sections in the storage. However, when the data is to be read from storage for utilization, the omitted repetitious sections must be inserted. This is accomplished by providing hardware apparatus which recognizes a particular flag occurring in the stored data. After recognizing the flag, the expansion apparatus interprets the next piece of information in the data stream as being the storage address of the start of a section of data that is to be inserted into the data stream; the next piece of information is interpreted as being the length of the section of data to be inserted; and the next following piece of information is the number of times that the section of data is to be inserted. The apparatus will respond to the flag and its associated indicators by inserting the appropriate data section the indicated number of times.
Description
~u DETAILED DESCRIPTION
21 ~ac~ground Of The Invention 22 This inventiDn relates to apparatus for expanding data 23 that has been compacted. More particularly, the invention 24 relates to apparatus for da~a expansion which is particularly useful in systems wherein long data sections of varying 26 lengths are repetitively used varying numbers of times.
27 In systems such as the one described in U. S. Patent 28 3,644,7ûO for "Method And Apparatus For Controlling An ~A'~' ~ . :
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1 Electron Beam" by R. V. Kruppa, long sections of the same
21 ~ac~ground Of The Invention 22 This inventiDn relates to apparatus for expanding data 23 that has been compacted. More particularly, the invention 24 relates to apparatus for da~a expansion which is particularly useful in systems wherein long data sections of varying 26 lengths are repetitively used varying numbers of times.
27 In systems such as the one described in U. S. Patent 28 3,644,7ûO for "Method And Apparatus For Controlling An ~A'~' ~ . :
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1 Electron Beam" by R. V. Kruppa, long sections of the same
2 data are repetitively used over and over again. The data
3 used to control an electron beam are typically stored
4 initialiy on a magnetic disk, from which they are read into in a memory buffer. From the buffer they are again read out 6 and used for control of the beam. In a typical prior art 7 system such as the one shown in the patent, beam control 8 data are read from a disk into the buffer, these data are used 9 for beam control, and then the next block of beam control data is read from the disk into the buffer. The amount of 11 time that is taken for reading data from the disk into the 12 buffer is a significant throughput limiting factor. Also, 13 a significant amount of space on the disks can be required 14 to hold all of the pattern data.
~rief Description Of The Invention 16 This invention provides apparatus for expanding 17 compacted data. In accordance with one aspect of the 18 invention, while reading from the buffer, the apparatus 19 responds to a particular configuration within the data stream, which configuration has replaced one or more repetitive data 21 sections. The cQpfiguration includes: a flag which uniquely 22 identifies it to~the apparatus; an address representing the 23 location in storage of the repetitive data section; the 24 length of the data section; and the number of times it is to be repeated. The expansion apparatus responds to the above 26 data format by inserting in place thereof the appropriate 27 beam control data.
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1074~)16 1 The primary advantage of this invention is that, by 2 permitting the buffer (and other intermediate storage 3 devices) to store compressed data, it enables the buffer 4 to store a larger amount of beam control data.
This leads to the further advantage that the buffer will 6 need to be refilled from a dis~ less often than would other-7 wise be necessary. Since the disk-to-buffer operation is 8 somewhat time consuming, use of this invention will increase 9 throughput in the type of system mentioned above.
It should also be noted that, ~ith this invention, the 11 compacted data need not contain any particular coded indica-12 tions of the beginning or end of sections of data. All of 13 the information neces~ary to locate the beginning and end 14 of a data section is contained in the information which immediately follows the identifying flagO This leads to 16 the additional advantage that the repetitive data sections 17 need not bear any particular relation to each other: that 18 is, any two particular data sections could be completely 19 separated from one another in storage, or they could partially overlap one another, or one could be completely included 21 within the other-22 The f~regoing and other features and advantages of the 23 invention will be apparent from the following more particular 24 description of preferred embodiments of the invention ag illustrated in the accompanying drawing.
26 In the drawings:
27 FIG. 1 is a schematic block diagram of a portion of an - 28 electron beam control system which embodies this inventiOn.
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' : ' ' ' ' '. ' ~. ' 1074~16 1 FIG. 2 shows an example of mechanism which could be used for keeping track of the length of a data section and of the number of times it has been inserted in the data stream.
FIG. 3 shows the format of the flag which is inserted into the data stream for compaction.
FIG. 4 is a flow diagram showing the sequence of opera-tion performed by a system embodying the invention.
FIG. 5 shows examples of compacted data.
Detailed Description FIG. 1 shows various aspects of a system embodying this invention. A storage unit 2 is presumed to contain compacted data which may have been loaded into it from a disk or other bulk storage medlum (not shown). Associated with the storage unit 2 is a storage data register SDR 4 th ~ gh which data moves out of the storage unit. The storage unit is addressed by a storage address register SAR 6. Data read from the storage unit 2 will be gated through gate 8 to some apparatus 10 which will use the data. This apparatus could, for example, be the pattern input buffer of an electron beam control system, the cen-tral processing unit of a computer, etc. As data goes out of storage, it is examined by a decoder 12 which continually checks for the particular pattern or pattèrns of bits that identify a situation where the data needs to be expanded.
This pattern is referred to as a "flag".
When the decoder 12 detects an expansion flag, it will produce a signal on line 14 to inhibit gate 8 from per-mitting passage of data from the storage 2 to the using apparatus 10. The same signal that was used to inhibit gate 8 will, via line 16, enable another gate 18 to cause data to be passed . .
- . ' 1074~16 1 from storage to a subrOutine register 20. As will be described 2 in more detail below, the data in subroutine register 20 3 will control insertion of repetitious data section~ into 4 the data stream.
In response to the flag, decoder 12 also causes the 6 cbntents of SAR 6 to be saved in an "old address register"
7 9AR 22. This will subsequently enable normal transmission 8 to resune at the proper address. Address information contained 9 in subroutine register 20 may be passed through an adder 24, where it may be combined with additio~al address information 11 contained in a base address register BAR 26, and into the 12 SAR 6. The decode mechanism 12 will then, via line 28, generate 13 a storage read signal. After subroutine register 20 has been 14 loaded, decoder 12 will generate signals on lines 14 and 16 to enable gate 8 (to pass data from storage 2 to the using 16 apparatus 10) and disable gate 18. Reading of data 17 from storage 2 to the using apparatus 10 will then commence.
18 Data will be read from the storage unit commencing at the 19 address supplied to the SAR 6. Information concerning the length of the data ~ection to be read, and the number 21 of times that it is to be read, will be supplied from the 22 subroutine regi~ter 20 to A subroutine con~rol mechanism 23 30.
24 After the appropriate data section has been inserted into the data stream from storage 2 to using apparatus 10 26 an appropriate number of times, the subroutine control 30 27 will cause the contents of OAR 22 to be transferred into 28 the SAR 6 and normal processing will again continue.
29 Referring now to FIG. 3, the format of an "instruction"
which causes data expansion is shown. (The word "instruction"
1074~116 1 is used in its very generic sense to refer to a pattern of 2 bits that initiates a particular action in the hardware 3 apparatus.) The înstruction comprises four fields utilizing 4 a total of forty-eight bits. The first eight bits are the flag which is detected by the decoder 12 to cause initiation 6 of data expansion. The next twenty-four bits represent the 7 starting address in storage of the data section that is to 8 be inserted in the data stream. The next twelve bits are 9 the length of the data section, and the-last four bits represent the number of times that the data section is to 11 be repeated. Using the configuration shown in FIG. 3, data 12 sections containing up to 4095 units of information may be 13 inserted as many as 15 times in response to one of these 14 instructions. The precise meaning of a "unit of information"
will depend upon the system in which this invention is 16 implemented, particularly upon the storage 2 and the manner -17 in which it is addressed. For example, the unit of information 18 could be a bit, a byte, a word, etc. The forty bits compris-19 ing thè address, length and count fields shown in FIG. 3 are the bits that are transmitted to the subroutine register 20 21 shown in FIG. 1.
22 Referring now to FIG. 2, there is shown one embodiment 23 of a mechanism that could be used to implement the subroutine 24 control 30. The length data held in subroutine register 20 will be transferred to a length register 32 and the count 26 information held in subroutine register 20 will be transferred 27 to a count register 34. During this transfer, both the 28 length and count fields will be checked by zero detect 29 circuits 36 and 38, respectively, to determine whether 1074~16 1 either or both of these fields contains a zero. In the 2 preferred embodiment of this invention, zeros in both the 3 length and count fields will be used to signify an uncon-4 ditional change in the contents of SAR 6 with subsequent continuation of processing. This is similar to a programmed 6 unconditional branch instruction. Zeros in both of these 7 fields will be detected by AND circuit 40 which will produce 8 the branch signal at its output. If one, but not both, of 9 the length and count fields contains a zero, an error condition will be signalled by the ~,output of Exclusive-Or 11 circuit 42.
12 If neither of the length and count fields is zero, 13 reading will commence from storage 2 at the address specified 14 in SAR 6. With each storage reference, a signal on line 44 will cause the contents of length register 32 to be decremented 16 by one. The decrement signal appearing on line 44 is preferably 17 derived through a delay 46 from the storage reference signal 18 which causes a readout from storage 2. Thus, the contents 19 of length register 32 will be decremented to "one'i a very short time after,the last data unit in the sequence has been 21 read from storag~. At this time, if count register 34 does 22 not contain a one, a signal from one-detector 48 will: pass 23 throùgh gate 50 to again set SAR 6 from the adder output latches 24 AOL of adder 24; pass through gate 52 to decrement the count register 34; and present a signal on line 54 to cause the 26 contents of length counter 32 to be set again from the subroutine 27 register 20. This sequence will continue until count register 28 34 is finally decremented to one.
1074~6 1 When count register 34 is decremented to one, one-detector 2 56 will produce a signal which inhibits gate 50 (preventing a 3 further attempt to set SAR 6 from the adder output latches) 4 and inhibits gate 52 (preventing further decrementation of count register 34). In order to prevent the possibility of 6 a "race condition" caused by premature occurrence of an 7 output from one-detector 56, it will be desirable to include 8 a delay 58 in the path of the signal which decrements count 9 register 34.
After count register 34 has been decremented to one, ~ -11 subsequent decrementation to one of length register 32 will 12 produce a concurrence of outputs from detectors 48 and 56, 13 both of which feed the inputs of AND 60. This concurrence 14 will result in a signal from AND 60 which will be utilized to transfer the contents of OAR 22 into SAR 6 so that the 16 system can proceed with normal transmission of data from 17 storage 2 to the using apparatus 10. (Those skilled in the 18 art will recognize that, depending upon the particular 19 environment in which this invention is implemented, the contents of OAR 22 will not necessarily be exactly the address 21 that needs to be!transferred in SAR 6 in order for normal 22 processing to co~tinue. However, in a typical sys~em, any 23 necessary alteration of the OAR 22 contents;prior to transfer 24 to the SAR 6 will simply be a matter of incrementing the contents of OAR 22 by a known fixed amount. One manner of 26 achieving this incrementation would be to insert an adder 62 27 in the path between SAR 6 and OAR 22 as shown in FIG. 1 so 28 that the addres3 going into OAR 22 is the address that will 29 actually be needed to subsequently return the ~ystem to its normal processing mode.) - - . ' . . :
lC~74016 1 All of the elements shown in FIG. 2 are items that are 2 well known in the art and need not be described in detail 3 herein. For example, detectors 36, 38, 48 and 56 could 4 simply be implemented as comparators, each of which receives a first input from an element as shown in FIG. 2. The second 6 input of each of the detectors 36 and 38 would be a fixed 7 zero; the second input of each of detectors 48 and 56 would 8 be A fixed one.
9 Referring now to FIG. 4, the sequence of operations of this invention is shown. As information is read from storage 11 (block 100) it is checked (block 102) to see whether or not 12 it contains a flag indicating that data expansion is required.
13 When a flag i8 detected, the output of the storage data 14 register will be inhibited from being transmitted to the using apparatus (block 104). The contents of the storage 16 address register will be transferred into the old address 17 register (block 106), with appropriate incrementing if 18 necessary. Approximately in parallel with the latter operation, 19 address, length and count information will be transferred to the subroutine register (block 108). The address information 21 in the subroutine~register will then, with any necessary 22 incrementation, be transferred to the storage address register 23 (block 110). The length and count information will be checked 24 to see if either or both is equal to zero (blocks 112, 114 and 116). If both are equal to zero, the sequence will return 26 to block 100 for continuation of normal data transmission 27 with a new address in the storage address register. If only 28 one of the length or count is equal to zero, an error signal , 1 will be generated. If neither the count nor the length is 2 equal to zero, a unit of data will be read from storage 3 (block 118). After reading a unit of data, if the length 4 register does not contain one (block 1201, it will be decremented (block 122) and another unit of data will be read 6 (block 118). When the length register does contain a one 7 (block 120), but the count register does not yet contain a 8 one (block 124); the count register will be decremented 9 (block 126), the length register will be set again from the subroutine register (block 128), and the storage address 11 register will be set (block 130) from the adder output latches 12 (or directly from the subroutine register if incrementation 13 capability is not included in the implementation) and the 14 first unit of data in the data sequence will again be read from storage (block 118). When the contents of the length 16 register has been decremented to one (block 120) after the 17 contents of the count register also has been decremented to 18 one (block 124) the data expansion will have been co~pleted.
19 Then, the contents of the old address register will be transferred to the storage address register (block 132) and 21 normal transmission of data from storage will continue (block 22 100).
23 Referring now to FIG. 5, manners are shown in which data 24 could have been compacted for use with this invention. The first line of FIG. 5 shows a data sequence ABCDCBACBABBDCD, 26 wherein each of the letters A, B, C and D represents a 27 different data sequence. Each of the four data sequences 28 represented in FIG. 5 may be of a different length, and each 29 is preferably somewhat longer than 48 bits (the length of the "instruction" which signals the apparatus to expand data).
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- ~ . . , 1074~16 1 As an example, we shall assume that data sequence A is twice 2 as long as an expand instruction; that B is four times as 3 long; that C is three times as long; and that D is five times 4 as long. Also as an example, and for ease in description, we will rëgard the length of an expand instruction as being 6 egual to one "unit". Thus, the sequence shown in the first 7 line of FIG. 5 (comprising three A's, five B's, four C's 8 and three D's) will occupy fifty-three units of storage if 9 it is stored in uncompacted form.
The second line of FIG. 5 shows ane manner in which this 11 data could have been compacted for u~e in a system~embodying 12 thi~ invention. The fifteen data sequences have been 13 compacted into four complete data sequences and nine expand 14 instructions, comprising a total of twenty-three units of storage - almost a fifty-seven percent saving. As shown in 16 the second line of FIG. 5, each of the sequences A, B, C and 17 D was included in its uncompacted form the first time that it 18 was encountered. After that, each time that one of the sequences 19 was encountered, it was replaced by a single expand lnstruction.
! In FIG. 5, each of the expand instructions is represented by 21 four lines indicating the four fields of the instruction.
22 The first line representg the flag which signals the apparatus 23 that expanBion i9 needed. The second line is the address of 24 the beginning of the data which is to be inserted in place of the ins'truction. For purposes of this example it has been 26 assumed that the data shown is located in contlguous storage 27 locations beginning at location zero. Thus, if the data were to 28 have been compacted as shown in the secona line of FIG. 5, data 29 segmont A would begin at location zero, data segment B would 1074~)16 1 begin at location two, data segment C would begin at location 2 six and data segment D would begin at location nine. In the 3 representations of instructions, the third line is the length 4 of the string of data that is to replace the instruction. For data segements A, B, C and D the lengths are 2, 4, 3 and 5, 6 respectively. Note that the last expand instruction, which 7 has replaced the compound data segment CD, shows a length of 8 eight, the sum of the lengths of C and D. The fourth line in 9 the representations of the expand instruction shows the number of times that the data segment is to be inserted. For the 11 instruction6 shown all of the counts equal one except for the 12 count in the instruction which replaces the compound data 13 segment BB, for which the count equals two.
14 The third line of FIG. 5 shows another manner in which the data could have been compacted prior to being utilized in a 16 system embodying this invention. Instead of utilizing an 17 uncompacted data sequence the first time that the sequence is 18 encountered, each of the sequences A, B and C is not shown in 19 expanded form until its second occurrence; the first occurrence of each of A, B and C is replaced by an expand instruction.
21 In this example, the address of the beginning of each of the 22 sequences A, B, C and D (assuming that the first expand 23 instruction is at location zero) are locations 15, 11, 8 and 24 3, respectively. This alternative form of compaction enables the data sequence CBA to be replaced by a single expand 26 instruction instead of the three instructions that were needed 27 in the previous example. This latter example of compaction 28 utilizes twenty-one units of storage: a saving of over 29 sixty percent over the uncompacted data; and a saving of almost nine percent as compared to the first example.
1074~16 1 Although the point is not illustrated in either of the 2 above examples, those skilled in the art will recognize that 3 savings in storage space can often be realized by including 4 some repetitious data segments more than once. For example, S if one had a situation where each of the compound data 6 segments AB, AC and AD were repeated several times, it could 7 be advantageous to include each of the three compound 8 segments in its uncompacted form even though this would g include three uncompacted A segments. Then, each of the three compound data segments could be replaced by a single expand 11 instruction, resulting in a net saving of storage space.
12 As was mentioned above in the description of FIG. 1, 13 an address which i8 transmitted from subroutine register 20 14 to SAR 6 may be incremented in an adqer 24 by the contents of a base address register BAR 26. This incrementation will 16 be particularly desirable in situations where, when the data 17 are originally compacted, the address of the block of storage 18 in which the data will ultimately reside is not precisely 19 known. In these situations, the address information that will be put in the expand instructions will comp~ise, for each data 21 segment, the disR~acement of that segment from the beginning 22 of a larger bloc~ of data. When the block of data is loaded 23 into storage 2, the storage address at which it begins will be ~ -24 loaded into BAR 26 via initial load line 64 so that, when 25 expansion i8 needed, appropriate addresses may be provided ~-26 through adder 24. By permitting blocks of data to be loaded 27 into different portions of storage at different times, this 28 enhances the flexibility of the system. An additional 29 enhancement to system flexibility may be provided by including : .
10740~6 1 an option as to whether or not addresses contained in sub-2 routine register 20 will be incremented by the contents of 3 BAR 26. This can be accomplished by utilizing two different 4 variations of the flag which identify the expand instruction~
One flag will be used when the address contained in the 6 expand instruction needs to be incremented by a base address 7 and, in this case, the apparatus will function as has been 8 described above. Another flag configuration can be used 9 to indicate that the address contained-in the expand instruc-tion is an absolute address that re~uires no incrementation.
11 In response to this latter flag, the decoder 12 can generate 12 a signal which is fed via an inhibit line 66 to a gate 68 to 13 prevent the contents of BAR 26 from being gated to the adder 14 24. Of course, other addressing schemes (for example, a virtual addressing system) could be used if desired.
16 Those skilled in the art will recognize that, in the 17 embodiment described in detail herein, data that are referred 18 to by an expand instruction should not contain another expand 19 instruction. The advantages potentially available with this invention could be increased by providing the ability to have 21 expand instructions within data that is, itself, referred 22 to by an expand nstruction. This could readily be accomplish-23 ed by adding additional subroutine registers 20 in series 24 with the one shown, and adding additional old address registers 22 in series with the one shown. If this were to be done, 26 it would also be desirable to add some checking circuitry 27 to insure that the retention capability of the OAR and 28 subroutine register stac~s is not exceeded by successive 29 expansion-within-expansion references. Such checking circuitry is not utilized in the embodiment described herein. One ~ , ~074016 1 manner in which checking could be inserted would utilize 2 a mode latch. When a flag is detected, the latch would be 3 set to indicate expand mode. After expansion is completed, 4 the latch would be reset. An error would be signalled if another flag was detected while the mode latch was set.
6 There are a large number of arrangements that could 7 be used for compacting the data, all of which can be used as 8 inputs to a system embodying this invention. For example, 9 in some applications it might be practical to maintain in storage at all times a fixed set of data patterns (which 11 could, but need not, comprise all of the data patterns 12 required for the application). ~his would eliminate the need 13 to repetitively reload such patterns into storage as the 14 data in storage are exhausted and new data are requested.
Any suitable methodology may be used for compacting 16 the data that are used as inputs to a system embodying this 17 invention. In a system such as the one described in the 18 Kruppa patent referred to above, the repetitive nature of 19 certain data segments will be readily observed when the input data are created and can easily be compacted at that time.
21 Those skill~d in the art will also recognize that the 22 "data" which are~used as inputs to this system could be of 23 various types such as, for example, numeric information or 24 computer programs. If the using apparatus were to be the execution unit of a digital computer, for example, this 26 invention could be utilized to cause the computer to execute 27 a particular subroutine that is outside the sequential 28 stream of instructions and to then automatically return to 29 the sequential instruction stream.
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1074~16 1 Although the preferred embodiments of this invention 2 recognize the end of a data expansion when both the length 3 and count have been decremented to "one", those skilled in 4 the art will recognize that other techniques, for example, decrementation to "zero" could also have been used.
6 F~rthermore, although this embodiment shows the use of a 7 length regiRter (32 in FIG. 2) which is decremented to a determine when the end of an expansion data segment has been 9 reached, the precise implementation of this portion of the invention will be determined to a large extent by the 11 environment in which the invention is implemented. Again, 12 details of such implementation are well known to those skilled 13 in the art and need not be expanded upon herein. ~
14 In the above embodiment, length was decremented when -storage was referenced. In a system wherein more than one 16 unit of data is set into the SDR, decremen~ation of length 17 would occur with each unit of data read from the SDR.
18 Although it will generally be desirable to have the 19 capability of incrementing addresses contained in the sub-routine register by the contents of a base address xegister, 21 in a relatively simple system wherein the absolute address 22 of each data segment is known beforehand, ~he inclusion of 23 a base address register and an adder (26 and 24, respectively, 24 in FIG. 1) might not be necessary.
Various requisites of any implementa~ion of this invention, 26 such as, for example, timing and gating signals, delays (to 27 avoid "race conditions"), etc. will be dependen~ upon the 28 details of the environment in which the invention is imple-29 mented. The size of the various fields in the expand 1074~16 1 instruction will depend upon details (such as op code 2 structure, memory size, etc.) of the environmental system.
3 Of course, the sequence of these fields could be charged 4 if desired. Also, in many implementations, various aspects of the invention that are shown, most particularly, in FIGS.
6 l and 2 will be somewhat distributed throughout the environ-7 mental system. For example, the decoder 12 (FIG. 1) would, 8 in many cases, actually be integrated within the control 9 store of a host system. The foregoing description of a preferred embodiment of the invention contains sufficient 11 information so that one skilled in the art would be able 12 to readily implement ~his invention in any given environment.
13 If this invention were implémented in a system wherein 14 memory read operations are terminated by a readout from a memory location specified in a termination register, there 16 would be no need for a length register (32 in FIG. 2) in 17 the subroutine control. The end of the data section could 18 be determined by adding the length held in the subroutine 19 register to the starting address also contained therein.
Alternatively, in such a system, the expand instruction could 21 contain the ending address instead of the length. However 22 the number of bits in a typical address is large enough 23 (compared to the'number of bits in a typical length field) so 24 that compaction efficiency would be adversely affected if -two complete addresses were used. Of course, the ending 26 addres~ (or, indeed, even the address used in the embodiment 27 described in detail above) could be a partial address, but 28 we prefer to avoid the slight additional complexities 29 that would be added if partial addresses were to be used.
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1074~16 1 While the invention has been particularly shown and 2 described with reference to a preferred embodiment thereof, 3 it will be understood by those skilled in the art that the 4 above and other changes in form and details may be made therein without departing from the spirit and scope of the 6 invention.
~rief Description Of The Invention 16 This invention provides apparatus for expanding 17 compacted data. In accordance with one aspect of the 18 invention, while reading from the buffer, the apparatus 19 responds to a particular configuration within the data stream, which configuration has replaced one or more repetitive data 21 sections. The cQpfiguration includes: a flag which uniquely 22 identifies it to~the apparatus; an address representing the 23 location in storage of the repetitive data section; the 24 length of the data section; and the number of times it is to be repeated. The expansion apparatus responds to the above 26 data format by inserting in place thereof the appropriate 27 beam control data.
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1074~)16 1 The primary advantage of this invention is that, by 2 permitting the buffer (and other intermediate storage 3 devices) to store compressed data, it enables the buffer 4 to store a larger amount of beam control data.
This leads to the further advantage that the buffer will 6 need to be refilled from a dis~ less often than would other-7 wise be necessary. Since the disk-to-buffer operation is 8 somewhat time consuming, use of this invention will increase 9 throughput in the type of system mentioned above.
It should also be noted that, ~ith this invention, the 11 compacted data need not contain any particular coded indica-12 tions of the beginning or end of sections of data. All of 13 the information neces~ary to locate the beginning and end 14 of a data section is contained in the information which immediately follows the identifying flagO This leads to 16 the additional advantage that the repetitive data sections 17 need not bear any particular relation to each other: that 18 is, any two particular data sections could be completely 19 separated from one another in storage, or they could partially overlap one another, or one could be completely included 21 within the other-22 The f~regoing and other features and advantages of the 23 invention will be apparent from the following more particular 24 description of preferred embodiments of the invention ag illustrated in the accompanying drawing.
26 In the drawings:
27 FIG. 1 is a schematic block diagram of a portion of an - 28 electron beam control system which embodies this inventiOn.
, :
- ~
' : ' ' ' ' '. ' ~. ' 1074~16 1 FIG. 2 shows an example of mechanism which could be used for keeping track of the length of a data section and of the number of times it has been inserted in the data stream.
FIG. 3 shows the format of the flag which is inserted into the data stream for compaction.
FIG. 4 is a flow diagram showing the sequence of opera-tion performed by a system embodying the invention.
FIG. 5 shows examples of compacted data.
Detailed Description FIG. 1 shows various aspects of a system embodying this invention. A storage unit 2 is presumed to contain compacted data which may have been loaded into it from a disk or other bulk storage medlum (not shown). Associated with the storage unit 2 is a storage data register SDR 4 th ~ gh which data moves out of the storage unit. The storage unit is addressed by a storage address register SAR 6. Data read from the storage unit 2 will be gated through gate 8 to some apparatus 10 which will use the data. This apparatus could, for example, be the pattern input buffer of an electron beam control system, the cen-tral processing unit of a computer, etc. As data goes out of storage, it is examined by a decoder 12 which continually checks for the particular pattern or pattèrns of bits that identify a situation where the data needs to be expanded.
This pattern is referred to as a "flag".
When the decoder 12 detects an expansion flag, it will produce a signal on line 14 to inhibit gate 8 from per-mitting passage of data from the storage 2 to the using apparatus 10. The same signal that was used to inhibit gate 8 will, via line 16, enable another gate 18 to cause data to be passed . .
- . ' 1074~16 1 from storage to a subrOutine register 20. As will be described 2 in more detail below, the data in subroutine register 20 3 will control insertion of repetitious data section~ into 4 the data stream.
In response to the flag, decoder 12 also causes the 6 cbntents of SAR 6 to be saved in an "old address register"
7 9AR 22. This will subsequently enable normal transmission 8 to resune at the proper address. Address information contained 9 in subroutine register 20 may be passed through an adder 24, where it may be combined with additio~al address information 11 contained in a base address register BAR 26, and into the 12 SAR 6. The decode mechanism 12 will then, via line 28, generate 13 a storage read signal. After subroutine register 20 has been 14 loaded, decoder 12 will generate signals on lines 14 and 16 to enable gate 8 (to pass data from storage 2 to the using 16 apparatus 10) and disable gate 18. Reading of data 17 from storage 2 to the using apparatus 10 will then commence.
18 Data will be read from the storage unit commencing at the 19 address supplied to the SAR 6. Information concerning the length of the data ~ection to be read, and the number 21 of times that it is to be read, will be supplied from the 22 subroutine regi~ter 20 to A subroutine con~rol mechanism 23 30.
24 After the appropriate data section has been inserted into the data stream from storage 2 to using apparatus 10 26 an appropriate number of times, the subroutine control 30 27 will cause the contents of OAR 22 to be transferred into 28 the SAR 6 and normal processing will again continue.
29 Referring now to FIG. 3, the format of an "instruction"
which causes data expansion is shown. (The word "instruction"
1074~116 1 is used in its very generic sense to refer to a pattern of 2 bits that initiates a particular action in the hardware 3 apparatus.) The înstruction comprises four fields utilizing 4 a total of forty-eight bits. The first eight bits are the flag which is detected by the decoder 12 to cause initiation 6 of data expansion. The next twenty-four bits represent the 7 starting address in storage of the data section that is to 8 be inserted in the data stream. The next twelve bits are 9 the length of the data section, and the-last four bits represent the number of times that the data section is to 11 be repeated. Using the configuration shown in FIG. 3, data 12 sections containing up to 4095 units of information may be 13 inserted as many as 15 times in response to one of these 14 instructions. The precise meaning of a "unit of information"
will depend upon the system in which this invention is 16 implemented, particularly upon the storage 2 and the manner -17 in which it is addressed. For example, the unit of information 18 could be a bit, a byte, a word, etc. The forty bits compris-19 ing thè address, length and count fields shown in FIG. 3 are the bits that are transmitted to the subroutine register 20 21 shown in FIG. 1.
22 Referring now to FIG. 2, there is shown one embodiment 23 of a mechanism that could be used to implement the subroutine 24 control 30. The length data held in subroutine register 20 will be transferred to a length register 32 and the count 26 information held in subroutine register 20 will be transferred 27 to a count register 34. During this transfer, both the 28 length and count fields will be checked by zero detect 29 circuits 36 and 38, respectively, to determine whether 1074~16 1 either or both of these fields contains a zero. In the 2 preferred embodiment of this invention, zeros in both the 3 length and count fields will be used to signify an uncon-4 ditional change in the contents of SAR 6 with subsequent continuation of processing. This is similar to a programmed 6 unconditional branch instruction. Zeros in both of these 7 fields will be detected by AND circuit 40 which will produce 8 the branch signal at its output. If one, but not both, of 9 the length and count fields contains a zero, an error condition will be signalled by the ~,output of Exclusive-Or 11 circuit 42.
12 If neither of the length and count fields is zero, 13 reading will commence from storage 2 at the address specified 14 in SAR 6. With each storage reference, a signal on line 44 will cause the contents of length register 32 to be decremented 16 by one. The decrement signal appearing on line 44 is preferably 17 derived through a delay 46 from the storage reference signal 18 which causes a readout from storage 2. Thus, the contents 19 of length register 32 will be decremented to "one'i a very short time after,the last data unit in the sequence has been 21 read from storag~. At this time, if count register 34 does 22 not contain a one, a signal from one-detector 48 will: pass 23 throùgh gate 50 to again set SAR 6 from the adder output latches 24 AOL of adder 24; pass through gate 52 to decrement the count register 34; and present a signal on line 54 to cause the 26 contents of length counter 32 to be set again from the subroutine 27 register 20. This sequence will continue until count register 28 34 is finally decremented to one.
1074~6 1 When count register 34 is decremented to one, one-detector 2 56 will produce a signal which inhibits gate 50 (preventing a 3 further attempt to set SAR 6 from the adder output latches) 4 and inhibits gate 52 (preventing further decrementation of count register 34). In order to prevent the possibility of 6 a "race condition" caused by premature occurrence of an 7 output from one-detector 56, it will be desirable to include 8 a delay 58 in the path of the signal which decrements count 9 register 34.
After count register 34 has been decremented to one, ~ -11 subsequent decrementation to one of length register 32 will 12 produce a concurrence of outputs from detectors 48 and 56, 13 both of which feed the inputs of AND 60. This concurrence 14 will result in a signal from AND 60 which will be utilized to transfer the contents of OAR 22 into SAR 6 so that the 16 system can proceed with normal transmission of data from 17 storage 2 to the using apparatus 10. (Those skilled in the 18 art will recognize that, depending upon the particular 19 environment in which this invention is implemented, the contents of OAR 22 will not necessarily be exactly the address 21 that needs to be!transferred in SAR 6 in order for normal 22 processing to co~tinue. However, in a typical sys~em, any 23 necessary alteration of the OAR 22 contents;prior to transfer 24 to the SAR 6 will simply be a matter of incrementing the contents of OAR 22 by a known fixed amount. One manner of 26 achieving this incrementation would be to insert an adder 62 27 in the path between SAR 6 and OAR 22 as shown in FIG. 1 so 28 that the addres3 going into OAR 22 is the address that will 29 actually be needed to subsequently return the ~ystem to its normal processing mode.) - - . ' . . :
lC~74016 1 All of the elements shown in FIG. 2 are items that are 2 well known in the art and need not be described in detail 3 herein. For example, detectors 36, 38, 48 and 56 could 4 simply be implemented as comparators, each of which receives a first input from an element as shown in FIG. 2. The second 6 input of each of the detectors 36 and 38 would be a fixed 7 zero; the second input of each of detectors 48 and 56 would 8 be A fixed one.
9 Referring now to FIG. 4, the sequence of operations of this invention is shown. As information is read from storage 11 (block 100) it is checked (block 102) to see whether or not 12 it contains a flag indicating that data expansion is required.
13 When a flag i8 detected, the output of the storage data 14 register will be inhibited from being transmitted to the using apparatus (block 104). The contents of the storage 16 address register will be transferred into the old address 17 register (block 106), with appropriate incrementing if 18 necessary. Approximately in parallel with the latter operation, 19 address, length and count information will be transferred to the subroutine register (block 108). The address information 21 in the subroutine~register will then, with any necessary 22 incrementation, be transferred to the storage address register 23 (block 110). The length and count information will be checked 24 to see if either or both is equal to zero (blocks 112, 114 and 116). If both are equal to zero, the sequence will return 26 to block 100 for continuation of normal data transmission 27 with a new address in the storage address register. If only 28 one of the length or count is equal to zero, an error signal , 1 will be generated. If neither the count nor the length is 2 equal to zero, a unit of data will be read from storage 3 (block 118). After reading a unit of data, if the length 4 register does not contain one (block 1201, it will be decremented (block 122) and another unit of data will be read 6 (block 118). When the length register does contain a one 7 (block 120), but the count register does not yet contain a 8 one (block 124); the count register will be decremented 9 (block 126), the length register will be set again from the subroutine register (block 128), and the storage address 11 register will be set (block 130) from the adder output latches 12 (or directly from the subroutine register if incrementation 13 capability is not included in the implementation) and the 14 first unit of data in the data sequence will again be read from storage (block 118). When the contents of the length 16 register has been decremented to one (block 120) after the 17 contents of the count register also has been decremented to 18 one (block 124) the data expansion will have been co~pleted.
19 Then, the contents of the old address register will be transferred to the storage address register (block 132) and 21 normal transmission of data from storage will continue (block 22 100).
23 Referring now to FIG. 5, manners are shown in which data 24 could have been compacted for use with this invention. The first line of FIG. 5 shows a data sequence ABCDCBACBABBDCD, 26 wherein each of the letters A, B, C and D represents a 27 different data sequence. Each of the four data sequences 28 represented in FIG. 5 may be of a different length, and each 29 is preferably somewhat longer than 48 bits (the length of the "instruction" which signals the apparatus to expand data).
FI9-76-021 -10- ~
' ~ ,".
- ~ . . , 1074~16 1 As an example, we shall assume that data sequence A is twice 2 as long as an expand instruction; that B is four times as 3 long; that C is three times as long; and that D is five times 4 as long. Also as an example, and for ease in description, we will rëgard the length of an expand instruction as being 6 egual to one "unit". Thus, the sequence shown in the first 7 line of FIG. 5 (comprising three A's, five B's, four C's 8 and three D's) will occupy fifty-three units of storage if 9 it is stored in uncompacted form.
The second line of FIG. 5 shows ane manner in which this 11 data could have been compacted for u~e in a system~embodying 12 thi~ invention. The fifteen data sequences have been 13 compacted into four complete data sequences and nine expand 14 instructions, comprising a total of twenty-three units of storage - almost a fifty-seven percent saving. As shown in 16 the second line of FIG. 5, each of the sequences A, B, C and 17 D was included in its uncompacted form the first time that it 18 was encountered. After that, each time that one of the sequences 19 was encountered, it was replaced by a single expand lnstruction.
! In FIG. 5, each of the expand instructions is represented by 21 four lines indicating the four fields of the instruction.
22 The first line representg the flag which signals the apparatus 23 that expanBion i9 needed. The second line is the address of 24 the beginning of the data which is to be inserted in place of the ins'truction. For purposes of this example it has been 26 assumed that the data shown is located in contlguous storage 27 locations beginning at location zero. Thus, if the data were to 28 have been compacted as shown in the secona line of FIG. 5, data 29 segmont A would begin at location zero, data segment B would 1074~)16 1 begin at location two, data segment C would begin at location 2 six and data segment D would begin at location nine. In the 3 representations of instructions, the third line is the length 4 of the string of data that is to replace the instruction. For data segements A, B, C and D the lengths are 2, 4, 3 and 5, 6 respectively. Note that the last expand instruction, which 7 has replaced the compound data segment CD, shows a length of 8 eight, the sum of the lengths of C and D. The fourth line in 9 the representations of the expand instruction shows the number of times that the data segment is to be inserted. For the 11 instruction6 shown all of the counts equal one except for the 12 count in the instruction which replaces the compound data 13 segment BB, for which the count equals two.
14 The third line of FIG. 5 shows another manner in which the data could have been compacted prior to being utilized in a 16 system embodying this invention. Instead of utilizing an 17 uncompacted data sequence the first time that the sequence is 18 encountered, each of the sequences A, B and C is not shown in 19 expanded form until its second occurrence; the first occurrence of each of A, B and C is replaced by an expand instruction.
21 In this example, the address of the beginning of each of the 22 sequences A, B, C and D (assuming that the first expand 23 instruction is at location zero) are locations 15, 11, 8 and 24 3, respectively. This alternative form of compaction enables the data sequence CBA to be replaced by a single expand 26 instruction instead of the three instructions that were needed 27 in the previous example. This latter example of compaction 28 utilizes twenty-one units of storage: a saving of over 29 sixty percent over the uncompacted data; and a saving of almost nine percent as compared to the first example.
1074~16 1 Although the point is not illustrated in either of the 2 above examples, those skilled in the art will recognize that 3 savings in storage space can often be realized by including 4 some repetitious data segments more than once. For example, S if one had a situation where each of the compound data 6 segments AB, AC and AD were repeated several times, it could 7 be advantageous to include each of the three compound 8 segments in its uncompacted form even though this would g include three uncompacted A segments. Then, each of the three compound data segments could be replaced by a single expand 11 instruction, resulting in a net saving of storage space.
12 As was mentioned above in the description of FIG. 1, 13 an address which i8 transmitted from subroutine register 20 14 to SAR 6 may be incremented in an adqer 24 by the contents of a base address register BAR 26. This incrementation will 16 be particularly desirable in situations where, when the data 17 are originally compacted, the address of the block of storage 18 in which the data will ultimately reside is not precisely 19 known. In these situations, the address information that will be put in the expand instructions will comp~ise, for each data 21 segment, the disR~acement of that segment from the beginning 22 of a larger bloc~ of data. When the block of data is loaded 23 into storage 2, the storage address at which it begins will be ~ -24 loaded into BAR 26 via initial load line 64 so that, when 25 expansion i8 needed, appropriate addresses may be provided ~-26 through adder 24. By permitting blocks of data to be loaded 27 into different portions of storage at different times, this 28 enhances the flexibility of the system. An additional 29 enhancement to system flexibility may be provided by including : .
10740~6 1 an option as to whether or not addresses contained in sub-2 routine register 20 will be incremented by the contents of 3 BAR 26. This can be accomplished by utilizing two different 4 variations of the flag which identify the expand instruction~
One flag will be used when the address contained in the 6 expand instruction needs to be incremented by a base address 7 and, in this case, the apparatus will function as has been 8 described above. Another flag configuration can be used 9 to indicate that the address contained-in the expand instruc-tion is an absolute address that re~uires no incrementation.
11 In response to this latter flag, the decoder 12 can generate 12 a signal which is fed via an inhibit line 66 to a gate 68 to 13 prevent the contents of BAR 26 from being gated to the adder 14 24. Of course, other addressing schemes (for example, a virtual addressing system) could be used if desired.
16 Those skilled in the art will recognize that, in the 17 embodiment described in detail herein, data that are referred 18 to by an expand instruction should not contain another expand 19 instruction. The advantages potentially available with this invention could be increased by providing the ability to have 21 expand instructions within data that is, itself, referred 22 to by an expand nstruction. This could readily be accomplish-23 ed by adding additional subroutine registers 20 in series 24 with the one shown, and adding additional old address registers 22 in series with the one shown. If this were to be done, 26 it would also be desirable to add some checking circuitry 27 to insure that the retention capability of the OAR and 28 subroutine register stac~s is not exceeded by successive 29 expansion-within-expansion references. Such checking circuitry is not utilized in the embodiment described herein. One ~ , ~074016 1 manner in which checking could be inserted would utilize 2 a mode latch. When a flag is detected, the latch would be 3 set to indicate expand mode. After expansion is completed, 4 the latch would be reset. An error would be signalled if another flag was detected while the mode latch was set.
6 There are a large number of arrangements that could 7 be used for compacting the data, all of which can be used as 8 inputs to a system embodying this invention. For example, 9 in some applications it might be practical to maintain in storage at all times a fixed set of data patterns (which 11 could, but need not, comprise all of the data patterns 12 required for the application). ~his would eliminate the need 13 to repetitively reload such patterns into storage as the 14 data in storage are exhausted and new data are requested.
Any suitable methodology may be used for compacting 16 the data that are used as inputs to a system embodying this 17 invention. In a system such as the one described in the 18 Kruppa patent referred to above, the repetitive nature of 19 certain data segments will be readily observed when the input data are created and can easily be compacted at that time.
21 Those skill~d in the art will also recognize that the 22 "data" which are~used as inputs to this system could be of 23 various types such as, for example, numeric information or 24 computer programs. If the using apparatus were to be the execution unit of a digital computer, for example, this 26 invention could be utilized to cause the computer to execute 27 a particular subroutine that is outside the sequential 28 stream of instructions and to then automatically return to 29 the sequential instruction stream.
~ . .
1074~16 1 Although the preferred embodiments of this invention 2 recognize the end of a data expansion when both the length 3 and count have been decremented to "one", those skilled in 4 the art will recognize that other techniques, for example, decrementation to "zero" could also have been used.
6 F~rthermore, although this embodiment shows the use of a 7 length regiRter (32 in FIG. 2) which is decremented to a determine when the end of an expansion data segment has been 9 reached, the precise implementation of this portion of the invention will be determined to a large extent by the 11 environment in which the invention is implemented. Again, 12 details of such implementation are well known to those skilled 13 in the art and need not be expanded upon herein. ~
14 In the above embodiment, length was decremented when -storage was referenced. In a system wherein more than one 16 unit of data is set into the SDR, decremen~ation of length 17 would occur with each unit of data read from the SDR.
18 Although it will generally be desirable to have the 19 capability of incrementing addresses contained in the sub-routine register by the contents of a base address xegister, 21 in a relatively simple system wherein the absolute address 22 of each data segment is known beforehand, ~he inclusion of 23 a base address register and an adder (26 and 24, respectively, 24 in FIG. 1) might not be necessary.
Various requisites of any implementa~ion of this invention, 26 such as, for example, timing and gating signals, delays (to 27 avoid "race conditions"), etc. will be dependen~ upon the 28 details of the environment in which the invention is imple-29 mented. The size of the various fields in the expand 1074~16 1 instruction will depend upon details (such as op code 2 structure, memory size, etc.) of the environmental system.
3 Of course, the sequence of these fields could be charged 4 if desired. Also, in many implementations, various aspects of the invention that are shown, most particularly, in FIGS.
6 l and 2 will be somewhat distributed throughout the environ-7 mental system. For example, the decoder 12 (FIG. 1) would, 8 in many cases, actually be integrated within the control 9 store of a host system. The foregoing description of a preferred embodiment of the invention contains sufficient 11 information so that one skilled in the art would be able 12 to readily implement ~his invention in any given environment.
13 If this invention were implémented in a system wherein 14 memory read operations are terminated by a readout from a memory location specified in a termination register, there 16 would be no need for a length register (32 in FIG. 2) in 17 the subroutine control. The end of the data section could 18 be determined by adding the length held in the subroutine 19 register to the starting address also contained therein.
Alternatively, in such a system, the expand instruction could 21 contain the ending address instead of the length. However 22 the number of bits in a typical address is large enough 23 (compared to the'number of bits in a typical length field) so 24 that compaction efficiency would be adversely affected if -two complete addresses were used. Of course, the ending 26 addres~ (or, indeed, even the address used in the embodiment 27 described in detail above) could be a partial address, but 28 we prefer to avoid the slight additional complexities 29 that would be added if partial addresses were to be used.
.
1074~16 1 While the invention has been particularly shown and 2 described with reference to a preferred embodiment thereof, 3 it will be understood by those skilled in the art that the 4 above and other changes in form and details may be made therein without departing from the spirit and scope of the 6 invention.
Claims (8)
1. Data expansion apparatus for processing data transmitted to a using device, comprising:
storage means having an output and containing locations storing a mixture of data and compact representations of data;
said compact representations of data each including a coded flag signifying that it is a compact representation;
an address field identifying the initial location in said storage means of a predetermined segment of data;
a length field indicating the length of said segment; and a count field indicating the number of repetitions of said segment to be sequentially transmitted to said using device;
gating means connecting the output of said storage means to said using device for transmission of data from said storage to said using device;
decoding means connected to the output of said storage means;
said decoding means being responsive to the occurrence of a flag at the output of said storage means to inhibit said gating means, thereby interrupting transmission of data from said storage means to said using device;
first register means;
means responsive to the occurrence at the output of said storage means of said address field, said length field and said count field to cause said first register means to store indications of the initial location, the length and the number of repetitions, respectively, of said segment;
said decoding means subsequently causing said gating means to be enabled;
means to cause transmission of said segment from said storage means to said using device; and control means responsive to the completion of transmission of said segment the number of times indicated by said count field and to cause recommencement of storage access from a storage location subsequent to the storage location storing a compact representation of data.
storage means having an output and containing locations storing a mixture of data and compact representations of data;
said compact representations of data each including a coded flag signifying that it is a compact representation;
an address field identifying the initial location in said storage means of a predetermined segment of data;
a length field indicating the length of said segment; and a count field indicating the number of repetitions of said segment to be sequentially transmitted to said using device;
gating means connecting the output of said storage means to said using device for transmission of data from said storage to said using device;
decoding means connected to the output of said storage means;
said decoding means being responsive to the occurrence of a flag at the output of said storage means to inhibit said gating means, thereby interrupting transmission of data from said storage means to said using device;
first register means;
means responsive to the occurrence at the output of said storage means of said address field, said length field and said count field to cause said first register means to store indications of the initial location, the length and the number of repetitions, respectively, of said segment;
said decoding means subsequently causing said gating means to be enabled;
means to cause transmission of said segment from said storage means to said using device; and control means responsive to the completion of transmission of said segment the number of times indicated by said count field and to cause recommencement of storage access from a storage location subsequent to the storage location storing a compact representation of data.
2. The data expansion apparatus of Claim 1 wherein said control means comprises:
first means for detecting the completion of transmission of said segment from said storage means to said using device;
second means for detecting that said segment has been transmitted the number of times indicated by said count field; and means jointly responsive to said first and second means for causing said recommencement.
FI9-76-021 CLAIMS 1 and 2
first means for detecting the completion of transmission of said segment from said storage means to said using device;
second means for detecting that said segment has been transmitted the number of times indicated by said count field; and means jointly responsive to said first and second means for causing said recommencement.
FI9-76-021 CLAIMS 1 and 2
3. The data expansion apparatus of Claim 2 wherein said first means comprises:
a length register;
means connecting said first register to said length register to cause said length register to store a repre-sentation of the length of said segment;
first decrementing means responsive to transmissions from said storage means to said using device to cause decrementation of said length register; and first detecting means connected to said length register for generating a first signal after said length register has been decremented to a first predetermined value.
a length register;
means connecting said first register to said length register to cause said length register to store a repre-sentation of the length of said segment;
first decrementing means responsive to transmissions from said storage means to said using device to cause decrementation of said length register; and first detecting means connected to said length register for generating a first signal after said length register has been decremented to a first predetermined value.
4. The data expansion apparatus of Claim 3 wherein said second means comprises:
a count register;
means connecting said first register to said count register to cause said count register to store a repre-sentation of the number of repetitions of said segment;
second decrementing means responsive to said first detecting means to cause decrementation of said count register each time said segment is transmitted from said storage means to said using device; and second detecting means connected to said count register for generating a second signal after said count register has been decremented to a second predetermined value.
FI9-76-021 CLAIMS 3 and 4
a count register;
means connecting said first register to said count register to cause said count register to store a repre-sentation of the number of repetitions of said segment;
second decrementing means responsive to said first detecting means to cause decrementation of said count register each time said segment is transmitted from said storage means to said using device; and second detecting means connected to said count register for generating a second signal after said count register has been decremented to a second predetermined value.
FI9-76-021 CLAIMS 3 and 4
5. The data expansion apparatus of Claim 4 wherein said control means further comprises:
means responsive to the presence of said first signal to cause said length register to store a representation of the length of said segment; and repeat means responsive to the presence of said first signal for causing retransmission of said segment from said storage means to said using device.
means responsive to the presence of said first signal to cause said length register to store a representation of the length of said segment; and repeat means responsive to the presence of said first signal for causing retransmission of said segment from said storage means to said using device.
6. The data expansion apparatus of Claim 5 wherein said control means further comprises:
means connecting said second detecting means to said repeat means and to said second decrementing means;
said second signal, when it occurs, inhibiting the operation of said repeat means and of said second decrementing means.
means connecting said second detecting means to said repeat means and to said second decrementing means;
said second signal, when it occurs, inhibiting the operation of said repeat means and of said second decrementing means.
7. The data expansion apparatus of Claim 5 wherein said control means further comprises:
error detecting means connected to said first register for generating an error signal in response to predetermined data configurations occurring in said first register.
error detecting means connected to said first register for generating an error signal in response to predetermined data configurations occurring in said first register.
8. The data expansion apparatus of Claim 7 wherein said error detecting means comprises:
means for detecting a predetermined value occurring in one, but not both, of said length and number of repetition indications stored in said first register.
FI9-76-021 CLAIMS 5, 6, 7 and 8
means for detecting a predetermined value occurring in one, but not both, of said length and number of repetition indications stored in said first register.
FI9-76-021 CLAIMS 5, 6, 7 and 8
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/701,325 US4054951A (en) | 1976-06-30 | 1976-06-30 | Data expansion apparatus |
Publications (1)
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|---|---|
| CA1074016A true CA1074016A (en) | 1980-03-18 |
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ID=24816911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA280,453A Expired CA1074016A (en) | 1976-06-30 | 1977-06-13 | Data expansion apparatus |
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| US (1) | US4054951A (en) |
| JP (1) | JPS533131A (en) |
| CA (1) | CA1074016A (en) |
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| FR (1) | FR2356999A1 (en) |
| GB (1) | GB1529538A (en) |
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| USRE36989E (en) * | 1979-10-18 | 2000-12-12 | Storage Technology Corporation | Virtual storage system and method |
| DE3118676A1 (en) * | 1981-05-12 | 1982-12-02 | Heinz Karl Eckhart Dr Jur | METHOD FOR COMPRESSING REDUNDANT FOLLOWS OF SERIAL DATA ELEMENTS |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3438003A (en) * | 1966-06-10 | 1969-04-08 | Bunker Ramo | Data compression system |
| US3717851A (en) * | 1971-03-03 | 1973-02-20 | Ibm | Processing of compacted data |
| CA1005916A (en) * | 1972-08-16 | 1977-02-22 | International Business Machines Corporation | Video compaction for printed text |
| DE2423817A1 (en) * | 1973-07-16 | 1975-02-06 | Ibm | METHOD AND CIRCUIT ARRANGEMENTS FOR CODING TWO-DIMENSIONAL PICTURE INFORMATION |
| US3946365A (en) * | 1973-12-13 | 1976-03-23 | Bantner John A | Graphic symbol generator |
| US3936808A (en) * | 1974-09-03 | 1976-02-03 | Ultronic Systems Corporation | Data storage and processing apparatus including processing of repeat character sequences |
| US3949377A (en) * | 1974-09-03 | 1976-04-06 | Ultronic Systems Corporation | Data storage and processing apparatus including processing of spacer characters |
-
1976
- 1976-06-30 US US05/701,325 patent/US4054951A/en not_active Expired - Lifetime
-
1977
- 1977-04-25 GB GB17020/77A patent/GB1529538A/en not_active Expired
- 1977-05-18 FR FR7716059A patent/FR2356999A1/en active Granted
- 1977-05-25 DE DE19772723523 patent/DE2723523A1/en not_active Withdrawn
- 1977-05-27 JP JP6129877A patent/JPS533131A/en active Granted
- 1977-06-13 CA CA280,453A patent/CA1074016A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2723523A1 (en) | 1978-01-05 |
| US4054951A (en) | 1977-10-18 |
| FR2356999A1 (en) | 1978-01-27 |
| GB1529538A (en) | 1978-10-25 |
| JPS5746096B2 (en) | 1982-10-01 |
| JPS533131A (en) | 1978-01-12 |
| FR2356999B1 (en) | 1979-03-09 |
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