CA1038500A - Scan and read control apparatus for a disk storage drive in a computer system - Google Patents
Scan and read control apparatus for a disk storage drive in a computer systemInfo
- Publication number
- CA1038500A CA1038500A CA209,551A CA209551A CA1038500A CA 1038500 A CA1038500 A CA 1038500A CA 209551 A CA209551 A CA 209551A CA 1038500 A CA1038500 A CA 1038500A
- Authority
- CA
- Canada
- Prior art keywords
- data
- disk
- scan
- field
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/48—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
- G11B5/58—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
- G11B5/596—Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S707/00—Data processing: database and file management or data structures
- Y10S707/99931—Database or file accessing
Abstract
SCAN AND READ CONTROL APPARATUS FOR A DISK STORAGE DRIVE IN A COMPUTER SYSTEM Control apparatus is provided for controlling a disk storage drive attachment in a computer system whereby records stored on the disk storage media are scanned and read within the same data field. The search key or search argument contained in main storage of the computer system is retrieved and compared with the key in the disk data field being scanned. The storage locations in the scan field not containing the search key are set to hexidecimal FF. The central processing unit (CPU) of the computer system is in a write to disk storage drive mode whereby the search argument is transferred from storage to the disk storage drive attachment as data is read from the disk storage drive. Decode apparatus senses the first hexidecimal FF from storage and switches the operation from a scan mode into a read mode and if a scan low or equal condition resulted from the comparison, the disk data field is read into the storage scan field with one byte of FF between the search key in storage and the newly stored disk data. The one byte of FF still provides an indication of the end of the search key. The operation then switches back to the scan mode and repeats in the manner described, i.e., sequential disk data fields are read into the storage scan field, until a comparison of equal or high results. When a high condition exists, a latch is set to block the storage of disk data in main storage because the storage scan field now contains the disk data field which had been sought, i.e., the one containing the desired index key.
Description
j / ~ ~-\
5~
1 Background of the Invention -, Field of -the Invention This invention relates to control circuitry in a com--'i / puter sys-tem and more particularly to control circuitry for controlling input/output operations in a computer system and still more particularly for controlling the scanning and -reading of data fields on disk media in a disk storage J~ drive.
~i~ Description of the Prior Art In the past it has been the practice to have a separate ~i key field and data field with a gap therebetween so as to facilitate switching from a scan mode when scanning the key ~-; f;eld to a read mode for reading the data field. The sepa-rate key field and gap wastes recording space. By elimi-nating the separate key field and ~,ap the data recording capacity is increased significantly. This increase in ~recording capacity; however, in the past has resulted in t` ~ lower system performance. This is because when performing a ~;~ scan operation, the search argument or key is compared only i~
~, 20 with the first key in the data field of one record. If the ~`
~-.3~ comparison is low, the search argument or key is then com- ~
1 , ~ .
. ,' pared with the first key in the data field oF the next ;iil record. If the comparison is high or equal then the key being sought must have been in the data field of the pre-vious record or in the record just scanned and another `3 revolution is required before the desired key can be read.This invention provides for switching from a scan ~,node ;'~ to a read mode within a data field whereby the desired key i~
is read within the same revolution. Hence, the invention ~ ;
~ ,'tj 30 improves system performance considerably.
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`., . _ ' ",'t"" R09-73-029 -2-.,.
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1 Summary of the Invention The principal objects of this invention are -to provide improved apparatus for comb;ning scan and read functions to .... .~.. : ~
:i enhance computer systems performance by eliminating disk :;~
storage rotational delays where the records on the disk :.
media do not have a separate key field with a gap between ' ~ the key and data fields. The invention provides a rela~
J
tively inexpensive combination of apparatus for combining $ the scan and read functions. ~;
` 10 The objects of the invention are achieved by providing . decode apparatus for detecting a hexidecimal FF transferred ;~
,` from the scan data field in main storage to the disk storage 7 drive attachment. The scan data field in main storage con~
,. ;, .
,:~ tains the search key at the head of the field and the re-mainder of the field is filled with hexidecimals FF. The ~.
` ~ scan operation takes place by transferr;ng the scan data field from main storage a byte at a time and comparing the .:. ;
search key from main storage with the key in the disk data ~ .
:~ field. The comparison takes place until the disk storage drive detects a hexidecimal FF byte. This indicates that .. -,. .i. , .
.. s. the comparison operation is complete and sets the operation .
~, from a scan mode ;nto a read mode whereby if the key of the ~:~
: .
:, disk data field compares low or equal to the search key, the ~ii rema;ning bytes in the disk data field are transferred into . the scan data field in main storage with one byte of hexi- .
:
', decimal FF between the search key in the scan field and the :
newly transferred bytes from the disk data field. This one ,.. :. . .
:~ byte of FF functions to absorb the switching time for .~?, changing from a scan to a read mode and it still delineates :~
d 30 the end of the search key. ~
.? The operation returns to the scan mode and if the -first ~.;
key of the next disk data field compares low:or equal to the z.l R09-73-029 -3-. :,;:; . : .
.,;'~, ~
... ~,,j . . : .
: ~: ,. . ..
. ~;,` .
1(~385~
1 storage s~arch key, the remdining bytes in the disk data field are transferred into the storage scan field to overlay the bytes transferred from the previous disk data field. If the first key in the nex-t clisk data field compares h;gh to ~: -the storage search key, the operation still switches from the scan to the read mode but the remaining bytes in the disk data field are blocked from entering Main storage.
This blocking action takes place because the key being sought from the disk data fields must already be in the scan field in main storage. ~`
Description of the Drawings Figs. la and lb taken together with Fig. la disposed to the left of Fig. lb represent a schematic block diagr-am of the ~nvention incorporated in a computer system, Fig. 2 is a schernatic logic diagram illustratiny the scan and read controls which are shown in block form in Fig. Ib, Fig. 3 is a diagram illustrating the scan field in main storage at the start of the scan and read operation, Fig. 4 is a diagram illustrating the scan field in main storage during the scan and read operation and after the disk data field has been transferred into the scan field, Fig. 5 is a diagram illustrating adjacent disk data fields, and Fig. 6 is a timing diagram.
Description The invention by way of example is shown in Figs. la ` ~`
and lb as being incorporated into a computer system of the type shown and described in the IBM* 5410 Processing Unit Theory of Operation Manual, SY31-0207-2, copyrighted by International Business Machines Corporation, 1971.
* Registered Trademark of International Business Machines ~orporation.
R09-73-029 _4_ - , , .. , .-. ,- . .: . .. . , , : -: .. . .. .
3850(1 ;~ ~
1 Figs. la and lb are substantially a modification of the drawing sho~ln on pa~e 2-015 of the IBM 5445 Disk Storage Drive Attachment for System/3 Theory - Maintenance Diagrams Manual, SY31-0311-0 copyrighted by International Business Machines Corporation, 1972.
' The scan read controls 100 in Fig. lb provide for both scanning and reading a disk data field during a single revolu-~ tion of the disk in the disk storage drive 200. The scan read ~
'~ :
controls 100 are part of the I/0 attachment 30 which attaches the disk storage drive 200 to the computer system consisting of main storage 10 and central processing unit (CPU) 15.
The scan and read operation is initiated when the CPU ;
, encounters a scan read instruction. The scan read instruc-~;~ tion is an I/0 instruction having an op code of hexidecimal ,;! F3. The specific Form oF the I/0 instruction ;s shown on q page 3-015 of the IBM 5445 Disk Storage Drive Attachment For System/3 Manual. The Q byte will be either hexidecimal CB
~' or C3 depending upon whether the M bit, i.e., bit 4 of the Q byte is a zero or one. If bit 4 is a zero, the removable disk drive is selected and if it is a one, the fixed disk 3 drive is selected. B;ts 5-7 inclusive of the Q byte are 011 respectively, to represent the scan field. Bit 4 of the R
byte of the instruction must be a one to indicate that the operation is a scan read operation.
~, The Q byte and R byte are transferred successively from J, -, CPU 15 over Data Bus Out 16 to DB0 register 20. The contents of the DB0 register 20 are decoded by operation control logic in block 31.
"~ .
Durin~ a scan read operation, main storage 10 is set up ~ -with a scan field as shown in Flg. 3. In this particular instance the search key in the scan field consists of three -~ ~-i bytes. A byte consists of 8 binary bits which are grouped ~, R09-73-029 _5_ ~03856~
1 together to represent data in either binar.y or hexidecimal form. These -terms are well known in the art and are des~
cribed in more detail in the aforementioned manuals. The .. .: ~.
search key can take any form and in this instance is repre-sented by numeric characters noooo2. This number, For example, could represent a customer identification number ~`
and the task would be to locate the data on disk file 200 which relates to that customer number. Disk file 200 has a master file index set forth in the form shown in Fig. 5.
The keys in the master file index are numbered sequentially and the key ID associated with the key indicates the loca-tion of the data on the disk in the disk storage drive 200 Hence, in this instance, the search key in the scan data field is used for locating the desired key in the master index file. Upon Finding the proper key in the disk data field, the key and the associated key ID are read into the scan field in main storage 10. This enables the issuance ~ .
of instructions for retrieving data fro~ the disk storage drive 200 at the location specified by the key ID which is : -.
now in storage. :~
Initially, the scan data field is set up with the search .
key at the head of the scan field followed by bytes of hexi~
decimal FF. Data is transFerred from main storage 10 to the ~:`
.: . .:.
CPU 15 and From there via Data Bus Out 16 to DBO register 20 one byte at a time. Thus, the first byte of data transferred : .:
from the scan field in main storage 10 enters DBO register 20 and from there it transfers via OR circuit 39 to Data Buffer -1 represented by reference character 40. A second byte of data is transferred in a similar manner to Data Buffer 2 represented by reference character 41. The transfer oF the first two data bytes is under control and at the request of the attachment 30 and takes place prior to the serializing .
: ., - .... :: , , ... , ~ .. ... .. .. . . . .. . .
~038500 : ~
l of data from the field of data being read in From thP disk -storage drive 200. The transFer of the first two bytes of data thus takes place while the read head o-f the disk stor- ~2 age drive 200 is in the gap area, Fig. 5, preceding the disk data field.
The byte of data in Buffer 40 is trans~erred to Data Store register 50 via Select logic 46 and ~ate register 47 just prior to reading the first byte of data from the disk data field. The byte of data in Data Store register 50 is then transferred to Write register 55. It should also be ;~
noted that during this transfer another byte of data, i.e., the third byte of data is fetched from main storage lO and transferred to Data Buffer ~0. A1so, after khe byte in Data Storage register 50 has b~en transferred to Write register 55 and the compare operation has started the second byte of -data in register ~l is transferred to Data Store register 50.
The compare operation takes place by simultaneously 1.' ~:
reading the byte of data in register 55 to Serializer 56 and ~
reading data bit by bit from disk storage drive 200 to Sepa- ~ ;
rator 58. The Separator 58 functions to shape the data bits coming from the disk storage drive 200 and passes the data bits to Compare logic 57 where they are compared serially with data bits from Serializer 56. After the last bit of ~ . ~
the first byte of data in Write reg;ster 55 has heen serial-ized and compared with a bit ~rom the disk storage drive 200, the results of the compare operation are stored in Compare logic 57 and the second byte of data which is in Date Store register is transferred to Write register 55. Data Store register 50 is th~en loaded with the third byte of data from register 40. Register ~l has already been loaded with a fourth byte of data from the scan field in main storage lO.
Then as previously described, the compare operation starts 10 ~ O!~
1 and Buffer 40 is loaded with the fifth byte of data. The `.
compare operation takes place in the same manner as pre~
viously described and the results thereof are stored in Com- ~ .
pare logic 57.
The operation just described continues until a hexideci-- mal FF is detected in the Write register 55. However, when .. the first hexidecimal FF enters DB0 register 20, it is ~ .
detected by the scan read controls 100. This detection is accomplished by AND circuit 108 in Fig. 2. AND circuit 108 `;~
detects when the bits in DB0 register 20 are all ones and is .
, . . .
gated by a Data Cycle Generate signal on conductor 122 and a .
Pull Mode signal on conductor 123. The Data Cycle Generate .
signal is developed within attachment 30, see page 8-205 of the IBM 5445 Disk Storage Drive Attachment for System/3 Manual and indicates that the attachment has requested a ~: `
cycle steal from CPU 15 and that the cycle steal has been : ;. .
granted and a byte of data is in the process of being trans~
ferred to the attachment 30. The Pull Mode signal is shown on page 8-085 of the IBM 5445 Disk Storage Drive Attachment ... :
~I 20 for System/3 Manual and it indicates that attachment 30 is pulling or asking for bytes of data from main storage 10 via CPU 15. Although at.tachment 30 is in the Pull Mode and data ;
is available for being written onto the disk in the disk storage drive 200, the Write Controls and Write Gate signals ': :
on conductors 70 and 71 are not present and therefore no data ~ . .
is being written on the disk. In fact, as previously men- .
~, tioned, data is being read from the disk to Separator 58.
: Reading takes place when the Write Gate is not present. ~: ~
The output of AND circuit 108 indlcating the detection : ~`
of hexidecimal FF conditions AND circuit 105 which also receives an input from AND circuit 103. AND circuit 105 con-.~. trols the setting of Scan Read FF latch 107. Thus, this latch .. R09-73-029 -8-.... . .c . .... . -. ~
,.,. ~ . , . .. . , ~ ,, . .. . .. ~ . . .
~ 3~5~
, 1 ~ill be set ~lhen the in~u-t con~itions to ~ID circuit, 103 and 108 have been met. AND circuit 103 receives a clock 6 signal from CPU timing bus 17 in Fig. la. It also receives the set output of Scan Read latch 102 and a Data Time signal on conduc-tor 125 from attachment 30, see page 8-045 of the IBM 5445 Disk Storage Drive Attachment for System/3 Manual.
The Data Time signal is a timing signal wh-ich starts at the end of CHR I0 field, Fig. 5, and ends at the end of the disk . . .
data field.
The Scan Read latch 102 is set under control of AND cir-cuit 101. This AND circuit receives a bit 4 signal from DB0 ~- register 20 on conductor 126. A SI0 IR Sample signal is ~;
passed by conductor 127 to AND circuit 101. The SI0 IR Sample ~ -signal comes from operation controls 31 and indicates that an IR cycle is taking place. AND circuit 101 also receives a . .
Scan Op signal on conductor 128. The Scan Op signal results from decodlng the N bits of the Q byte, see page 3-065 of . ~
the IBM 5445 D;sk Storage Drive Attachment for System/3 Manual.
From the foregoing, lt is seen that the Scan Read FF FF
latch 107 is set when in the scan read operation, i.e., after the Scan Read latch 102 has been set and AND circuit 108 has detected the first FF byte placed into DB0 register 20 when operating in a pu11 mode. Of course, since the FF byte was put in the DB0 register 20, it ls also transFerred to one of the Data Buffers 40 or 41, depending upon which bufFer is in condition for receiving it. The hexidecimal FF byte of data ; is then transferred from the Data Buffers 40 or 41 to the Data Storage register 50 and from there to Write register 55 in the same manner as previously described for other bytes of data. When the Scan Read FF latch 107 is set, it is necessary to inhibit transfer of a byte of data from the scan Field to DB0 register 20 and to inhibit incrementing the scan field 1 address in the DDDR register in the CPU 15. It is important not to change khe address in the DDDR because the by-te of data combtng from the disk data field must be transferred to the scan field in main storage at the address in the DDDR which `~
is the byte position adjacent to the first byte of hexideci~
. ~ ; . . ~
mal FF. The signal for inhibiting the transfer of the next byte from the scan field is the Scan Read FF signal from latch k 107 which is applied to inverter 145. This causes AND circuit 146 to be de-conditioned. AND circuit 146 receives a Cycle Request 1 signal from Buffer and Cycle Steal Controls 85 and its output is a Cycle Req 1 signal. The Cycle Req 1 signal ;~
is the signal which causes a transfer of a byte of data from ? main storage 10 to the Data Buffers 40 or 41. The Scan Read 1st FF signal also inhibits the incrementin9 of the Address , , : :, .
;' in the DDDR because no cycle steal is taken. ~
.i , ! In order to prevent an over run condition, it ls neces- `
~ sary to prevent the cycle steal logic in controls 85 from ~`
5~
1 Background of the Invention -, Field of -the Invention This invention relates to control circuitry in a com--'i / puter sys-tem and more particularly to control circuitry for controlling input/output operations in a computer system and still more particularly for controlling the scanning and -reading of data fields on disk media in a disk storage J~ drive.
~i~ Description of the Prior Art In the past it has been the practice to have a separate ~i key field and data field with a gap therebetween so as to facilitate switching from a scan mode when scanning the key ~-; f;eld to a read mode for reading the data field. The sepa-rate key field and gap wastes recording space. By elimi-nating the separate key field and ~,ap the data recording capacity is increased significantly. This increase in ~recording capacity; however, in the past has resulted in t` ~ lower system performance. This is because when performing a ~;~ scan operation, the search argument or key is compared only i~
~, 20 with the first key in the data field of one record. If the ~`
~-.3~ comparison is low, the search argument or key is then com- ~
1 , ~ .
. ,' pared with the first key in the data field oF the next ;iil record. If the comparison is high or equal then the key being sought must have been in the data field of the pre-vious record or in the record just scanned and another `3 revolution is required before the desired key can be read.This invention provides for switching from a scan ~,node ;'~ to a read mode within a data field whereby the desired key i~
is read within the same revolution. Hence, the invention ~ ;
~ ,'tj 30 improves system performance considerably.
', t; ,l-c,fi~
. . . t ~f .,~
`., . _ ' ",'t"" R09-73-029 -2-.,.
. ~, . ' !.
: -.i, Q ~ : :
1 Summary of the Invention The principal objects of this invention are -to provide improved apparatus for comb;ning scan and read functions to .... .~.. : ~
:i enhance computer systems performance by eliminating disk :;~
storage rotational delays where the records on the disk :.
media do not have a separate key field with a gap between ' ~ the key and data fields. The invention provides a rela~
J
tively inexpensive combination of apparatus for combining $ the scan and read functions. ~;
` 10 The objects of the invention are achieved by providing . decode apparatus for detecting a hexidecimal FF transferred ;~
,` from the scan data field in main storage to the disk storage 7 drive attachment. The scan data field in main storage con~
,. ;, .
,:~ tains the search key at the head of the field and the re-mainder of the field is filled with hexidecimals FF. The ~.
` ~ scan operation takes place by transferr;ng the scan data field from main storage a byte at a time and comparing the .:. ;
search key from main storage with the key in the disk data ~ .
:~ field. The comparison takes place until the disk storage drive detects a hexidecimal FF byte. This indicates that .. -,. .i. , .
.. s. the comparison operation is complete and sets the operation .
~, from a scan mode ;nto a read mode whereby if the key of the ~:~
: .
:, disk data field compares low or equal to the search key, the ~ii rema;ning bytes in the disk data field are transferred into . the scan data field in main storage with one byte of hexi- .
:
', decimal FF between the search key in the scan field and the :
newly transferred bytes from the disk data field. This one ,.. :. . .
:~ byte of FF functions to absorb the switching time for .~?, changing from a scan to a read mode and it still delineates :~
d 30 the end of the search key. ~
.? The operation returns to the scan mode and if the -first ~.;
key of the next disk data field compares low:or equal to the z.l R09-73-029 -3-. :,;:; . : .
.,;'~, ~
... ~,,j . . : .
: ~: ,. . ..
. ~;,` .
1(~385~
1 storage s~arch key, the remdining bytes in the disk data field are transferred into the storage scan field to overlay the bytes transferred from the previous disk data field. If the first key in the nex-t clisk data field compares h;gh to ~: -the storage search key, the operation still switches from the scan to the read mode but the remaining bytes in the disk data field are blocked from entering Main storage.
This blocking action takes place because the key being sought from the disk data fields must already be in the scan field in main storage. ~`
Description of the Drawings Figs. la and lb taken together with Fig. la disposed to the left of Fig. lb represent a schematic block diagr-am of the ~nvention incorporated in a computer system, Fig. 2 is a schernatic logic diagram illustratiny the scan and read controls which are shown in block form in Fig. Ib, Fig. 3 is a diagram illustrating the scan field in main storage at the start of the scan and read operation, Fig. 4 is a diagram illustrating the scan field in main storage during the scan and read operation and after the disk data field has been transferred into the scan field, Fig. 5 is a diagram illustrating adjacent disk data fields, and Fig. 6 is a timing diagram.
Description The invention by way of example is shown in Figs. la ` ~`
and lb as being incorporated into a computer system of the type shown and described in the IBM* 5410 Processing Unit Theory of Operation Manual, SY31-0207-2, copyrighted by International Business Machines Corporation, 1971.
* Registered Trademark of International Business Machines ~orporation.
R09-73-029 _4_ - , , .. , .-. ,- . .: . .. . , , : -: .. . .. .
3850(1 ;~ ~
1 Figs. la and lb are substantially a modification of the drawing sho~ln on pa~e 2-015 of the IBM 5445 Disk Storage Drive Attachment for System/3 Theory - Maintenance Diagrams Manual, SY31-0311-0 copyrighted by International Business Machines Corporation, 1972.
' The scan read controls 100 in Fig. lb provide for both scanning and reading a disk data field during a single revolu-~ tion of the disk in the disk storage drive 200. The scan read ~
'~ :
controls 100 are part of the I/0 attachment 30 which attaches the disk storage drive 200 to the computer system consisting of main storage 10 and central processing unit (CPU) 15.
The scan and read operation is initiated when the CPU ;
, encounters a scan read instruction. The scan read instruc-~;~ tion is an I/0 instruction having an op code of hexidecimal ,;! F3. The specific Form oF the I/0 instruction ;s shown on q page 3-015 of the IBM 5445 Disk Storage Drive Attachment For System/3 Manual. The Q byte will be either hexidecimal CB
~' or C3 depending upon whether the M bit, i.e., bit 4 of the Q byte is a zero or one. If bit 4 is a zero, the removable disk drive is selected and if it is a one, the fixed disk 3 drive is selected. B;ts 5-7 inclusive of the Q byte are 011 respectively, to represent the scan field. Bit 4 of the R
byte of the instruction must be a one to indicate that the operation is a scan read operation.
~, The Q byte and R byte are transferred successively from J, -, CPU 15 over Data Bus Out 16 to DB0 register 20. The contents of the DB0 register 20 are decoded by operation control logic in block 31.
"~ .
Durin~ a scan read operation, main storage 10 is set up ~ -with a scan field as shown in Flg. 3. In this particular instance the search key in the scan field consists of three -~ ~-i bytes. A byte consists of 8 binary bits which are grouped ~, R09-73-029 _5_ ~03856~
1 together to represent data in either binar.y or hexidecimal form. These -terms are well known in the art and are des~
cribed in more detail in the aforementioned manuals. The .. .: ~.
search key can take any form and in this instance is repre-sented by numeric characters noooo2. This number, For example, could represent a customer identification number ~`
and the task would be to locate the data on disk file 200 which relates to that customer number. Disk file 200 has a master file index set forth in the form shown in Fig. 5.
The keys in the master file index are numbered sequentially and the key ID associated with the key indicates the loca-tion of the data on the disk in the disk storage drive 200 Hence, in this instance, the search key in the scan data field is used for locating the desired key in the master index file. Upon Finding the proper key in the disk data field, the key and the associated key ID are read into the scan field in main storage 10. This enables the issuance ~ .
of instructions for retrieving data fro~ the disk storage drive 200 at the location specified by the key ID which is : -.
now in storage. :~
Initially, the scan data field is set up with the search .
key at the head of the scan field followed by bytes of hexi~
decimal FF. Data is transFerred from main storage 10 to the ~:`
.: . .:.
CPU 15 and From there via Data Bus Out 16 to DBO register 20 one byte at a time. Thus, the first byte of data transferred : .:
from the scan field in main storage 10 enters DBO register 20 and from there it transfers via OR circuit 39 to Data Buffer -1 represented by reference character 40. A second byte of data is transferred in a similar manner to Data Buffer 2 represented by reference character 41. The transfer oF the first two data bytes is under control and at the request of the attachment 30 and takes place prior to the serializing .
: ., - .... :: , , ... , ~ .. ... .. .. . . . .. . .
~038500 : ~
l of data from the field of data being read in From thP disk -storage drive 200. The transFer of the first two bytes of data thus takes place while the read head o-f the disk stor- ~2 age drive 200 is in the gap area, Fig. 5, preceding the disk data field.
The byte of data in Buffer 40 is trans~erred to Data Store register 50 via Select logic 46 and ~ate register 47 just prior to reading the first byte of data from the disk data field. The byte of data in Data Store register 50 is then transferred to Write register 55. It should also be ;~
noted that during this transfer another byte of data, i.e., the third byte of data is fetched from main storage lO and transferred to Data Buffer ~0. A1so, after khe byte in Data Storage register 50 has b~en transferred to Write register 55 and the compare operation has started the second byte of -data in register ~l is transferred to Data Store register 50.
The compare operation takes place by simultaneously 1.' ~:
reading the byte of data in register 55 to Serializer 56 and ~
reading data bit by bit from disk storage drive 200 to Sepa- ~ ;
rator 58. The Separator 58 functions to shape the data bits coming from the disk storage drive 200 and passes the data bits to Compare logic 57 where they are compared serially with data bits from Serializer 56. After the last bit of ~ . ~
the first byte of data in Write reg;ster 55 has heen serial-ized and compared with a bit ~rom the disk storage drive 200, the results of the compare operation are stored in Compare logic 57 and the second byte of data which is in Date Store register is transferred to Write register 55. Data Store register 50 is th~en loaded with the third byte of data from register 40. Register ~l has already been loaded with a fourth byte of data from the scan field in main storage lO.
Then as previously described, the compare operation starts 10 ~ O!~
1 and Buffer 40 is loaded with the fifth byte of data. The `.
compare operation takes place in the same manner as pre~
viously described and the results thereof are stored in Com- ~ .
pare logic 57.
The operation just described continues until a hexideci-- mal FF is detected in the Write register 55. However, when .. the first hexidecimal FF enters DB0 register 20, it is ~ .
detected by the scan read controls 100. This detection is accomplished by AND circuit 108 in Fig. 2. AND circuit 108 `;~
detects when the bits in DB0 register 20 are all ones and is .
, . . .
gated by a Data Cycle Generate signal on conductor 122 and a .
Pull Mode signal on conductor 123. The Data Cycle Generate .
signal is developed within attachment 30, see page 8-205 of the IBM 5445 Disk Storage Drive Attachment for System/3 Manual and indicates that the attachment has requested a ~: `
cycle steal from CPU 15 and that the cycle steal has been : ;. .
granted and a byte of data is in the process of being trans~
ferred to the attachment 30. The Pull Mode signal is shown on page 8-085 of the IBM 5445 Disk Storage Drive Attachment ... :
~I 20 for System/3 Manual and it indicates that attachment 30 is pulling or asking for bytes of data from main storage 10 via CPU 15. Although at.tachment 30 is in the Pull Mode and data ;
is available for being written onto the disk in the disk storage drive 200, the Write Controls and Write Gate signals ': :
on conductors 70 and 71 are not present and therefore no data ~ . .
is being written on the disk. In fact, as previously men- .
~, tioned, data is being read from the disk to Separator 58.
: Reading takes place when the Write Gate is not present. ~: ~
The output of AND circuit 108 indlcating the detection : ~`
of hexidecimal FF conditions AND circuit 105 which also receives an input from AND circuit 103. AND circuit 105 con-.~. trols the setting of Scan Read FF latch 107. Thus, this latch .. R09-73-029 -8-.... . .c . .... . -. ~
,.,. ~ . , . .. . , ~ ,, . .. . .. ~ . . .
~ 3~5~
, 1 ~ill be set ~lhen the in~u-t con~itions to ~ID circuit, 103 and 108 have been met. AND circuit 103 receives a clock 6 signal from CPU timing bus 17 in Fig. la. It also receives the set output of Scan Read latch 102 and a Data Time signal on conduc-tor 125 from attachment 30, see page 8-045 of the IBM 5445 Disk Storage Drive Attachment for System/3 Manual.
The Data Time signal is a timing signal wh-ich starts at the end of CHR I0 field, Fig. 5, and ends at the end of the disk . . .
data field.
The Scan Read latch 102 is set under control of AND cir-cuit 101. This AND circuit receives a bit 4 signal from DB0 ~- register 20 on conductor 126. A SI0 IR Sample signal is ~;
passed by conductor 127 to AND circuit 101. The SI0 IR Sample ~ -signal comes from operation controls 31 and indicates that an IR cycle is taking place. AND circuit 101 also receives a . .
Scan Op signal on conductor 128. The Scan Op signal results from decodlng the N bits of the Q byte, see page 3-065 of . ~
the IBM 5445 D;sk Storage Drive Attachment for System/3 Manual.
From the foregoing, lt is seen that the Scan Read FF FF
latch 107 is set when in the scan read operation, i.e., after the Scan Read latch 102 has been set and AND circuit 108 has detected the first FF byte placed into DB0 register 20 when operating in a pu11 mode. Of course, since the FF byte was put in the DB0 register 20, it ls also transFerred to one of the Data Buffers 40 or 41, depending upon which bufFer is in condition for receiving it. The hexidecimal FF byte of data ; is then transferred from the Data Buffers 40 or 41 to the Data Storage register 50 and from there to Write register 55 in the same manner as previously described for other bytes of data. When the Scan Read FF latch 107 is set, it is necessary to inhibit transfer of a byte of data from the scan Field to DB0 register 20 and to inhibit incrementing the scan field 1 address in the DDDR register in the CPU 15. It is important not to change khe address in the DDDR because the by-te of data combtng from the disk data field must be transferred to the scan field in main storage at the address in the DDDR which `~
is the byte position adjacent to the first byte of hexideci~
. ~ ; . . ~
mal FF. The signal for inhibiting the transfer of the next byte from the scan field is the Scan Read FF signal from latch k 107 which is applied to inverter 145. This causes AND circuit 146 to be de-conditioned. AND circuit 146 receives a Cycle Request 1 signal from Buffer and Cycle Steal Controls 85 and its output is a Cycle Req 1 signal. The Cycle Req 1 signal ;~
is the signal which causes a transfer of a byte of data from ? main storage 10 to the Data Buffers 40 or 41. The Scan Read 1st FF signal also inhibits the incrementin9 of the Address , , : :, .
;' in the DDDR because no cycle steal is taken. ~
.i , ! In order to prevent an over run condition, it ls neces- `
~ sary to prevent the cycle steal logic in controls 85 from ~`
2~ indicating that insufficient cycle steals requests have ~
:
occurred. A dummy cycle steal request is generated and sent to the Buffer Controls and Cycle Steal Controls 85. The i logic for generating the dummy cycle steal request includes - AND circuit 147 which controls the setting of Dummy Cycle ,;
Steal latch 148. AND circuit 147 has inputs for receiving the Cycle Request 1 signal, the Scan Read 1st FF signal and a clock 3 signal. The output of latch 148 is applied to OR ;
circuit 150 which also has an input for receiving the Data ,~ , . .
~ Cycle Generate signal. The output from OR circuit 150 is a ;~ signal applied to Buffer and Cycle Steal Controls 85 for in- ~`
~ dicating that Buffers 40 and 41 are full. Latch 148 is reset }
by the output of OR circuit 149. OR circuit 149 receives a clock 7 signal and a not Data Time Signal.
.; , . ..
Decode loqic 75 detects when the hexidecimal FF byte of ;~
"
~, . .
,, .
r 1 data is in the ~Irite register 55. The decode logic ~5 in res~
ponse to detecting the hexidecimal FF byte of data in Write register 55 generates a Write Reg FF signal on conductor 130 which is applied to AND circuit 109 in Fig. 2. AND circui-t 109 is also connected to receive the set output oF the Scan Read FF latch 107 and a Field Time signal on conductor 129.
The Field Time signal is a timing signal coming from attach-ment 30, see page 8-0~5 of the IBM 5445 Disk Storage Drive Attachment for System/3 Manual. AND circuit 109 provides a signal which is used -For switching from a scan mode, i.e., '! a pull mode into a read mode, i.e., a push mode. The signal , from AND circuit 109 is applied to AND circuit 113 which con- `
trols the setting of the Switch Modes latch 115. A~ID circuit 113 is gated or conditioned by a Bit Time 1 signal which comes from attachment 30 over Bit Times bus 76, Fig. lb. The bit time 1 signal in Fig. 2 is shown as being applied to conduc-tor 77 which forms a part of bus 76.
:! The set output of latch 115 is used for several purposes.
First, it is used to block buffer action request by providing a Block Buffer Action Req signal over conductor 135 to Buffer and Cycle Steal Controls 85 of Fig. la. The signal on conduc-tor 135 causes the Buffer and Cycle Steal Controls 85 to gener-ate a signal for preventing the transfer of data from either Data Buffer ~0 or ~1 to the Data Store register 50. Th;s action is necessary to prevent a data over run condition in the Buffer Control Logic 85.
~t Before the deserialized byte of data is transferred, it is necessary to reset Pull Mode. The reset signal for the Pull Mode is passed by AND circuit 117 which is connected to the set output of latch 115 and also receives a Bit Time ~ on conductor 78. The Reset Pull Mode signal from AND circuit 117 is also passed by OR circuit 120 as a Wrong Sync Restart . :
1~3~i~
or S~litch signal For resettin~J a serialize l~tch, see page 8-080 oF the IBM 5445 Disk Drive Attachment for Systeml3 `~
manual to stop the serializiny opera-tion and stopping the compare operation in the attachment 30. The Deserialize latch in the Select logic 46 of attachment 30 is se-t when `
attachment 30 receives a Switch Mode signal on conductor ~;
136, i.e., when Switch Modes latch 115 is set. The set out~
put of latch 115 is also applied to AND circuit 118 which controls the setting of the Block Data Store latch 119.
However, AND circuit 118 is condi tioned only when Compare `'' '"!. ~' logic 57 provides a scan high compare signal on conductor 137- Tn this instance, the resul ts of the compare operation are such that the scan high compare signal is not generated. ` `~
The Reset Pull Mode signal from AND circuit 117 is also used to reset the Scan Read FF latch 107 via OR circuit 106.
However, it should be noted that before latch 107 was reset latch 116 was set. The set output of latch 116 is applied ;~
to AND circuit 121 which also receives a Select Key Length signal on conductor 138. The Select Key Length signal comes from Buffer and Cycle steal controls 85, see page 8-215 of the IBM 5445 Disk Storage Drive Attachment for System/3 Manual. The output of AND circuit 121 provides a Subtract 1 ~ 1 from Disk Drive Data Register (DDDR) which is a local store register in CPU 15. The Subtract 1 from the Disk Drive Data Register (DDDR) is used to cause proper addressing of the scan field in main storage 10. The additional decrement is -., .: . ~
necessary because of one hexidecimal FF byte which is used to separate the search key from the disk data field which is placed in main storage In ~ manner which will now be described. -~
With the operation switched from the Pull Mode into the ` ,~
Read Mode and with the Deserialize Latch in Buffer and Cycle Steal Controls 85 set, a deserialized byte of clata is trans-:
:
~:
~0385~0 :~`
1 ferred from Deserializer 59 to Read Register 60 and from there through Select lo~ic 46, register 47 to Data Buffers 40 or 41.
The byte of data is then i;ransferred from data buffer 40 or 41 to DBI register 52. The byte of data in DBI register 62 is then transferred to main storage 10 via Data Bus In 63 and `3 CPU 15 at a location specified by the address in the DDDR
` register. Successive deserialized bytes of data are trans-ferred in a similar manner.
The number of bytes transferred is determined by the ~' 10 value in the Data Length register 44 during the time the ID
field was being read by the disk storage drive 200. Each time that a byte of data is transferred into main storage 10, the value in a counter in the Buffer and Cycle Steal controls 85 is decremented by 1. The operation continues until the ~, entire disk data field is transferred into main storage 10.
The data transfer is complete when the Data Time signal on , conductor 125 ls no longer present. This causes inverter 104 ;~ to provide a signal for resetting latch 107 via OR circuit 106, for resetting latch 115 vla OR circult 114 and for resetting latches 116 and 119. Latch 102 is not reset at :
this time because the scan read operation is not complete.
The scan read operation is not complete until a scan high condition has been detected or other predesignated conditions have come into being.
The operation again switches into a pull mode during the gap time preceding the next disk data field. The opera-i~ tion then continues in a manner as previously described. If ', the results of the compare operation still do not provide a -~
.i scan high compare signal on conductor 137 in Fig. 2, the newly transferred data would be entered into main storage 10 so as to overlay the data which had been entered into the ~ `~
scan field from the previous disk data field. With refer-,ii, R09-73-029 -13-:~`
~31~5~
l ence to Figs. 3 and 4, it s~ould be noted that the search ~ ;
key in the scan field is separated by a byte of hexidecimal ;
FF from the disk data field which has been en-tered into the scan field. This byte of hexidecimal FF continues to indi~
cate that the compare operation is to no longer take place and provides the necessary signals for conditioning AND~ ~ "~'!.
circuit 108 so as to initiate the switching from the pull mode into a read mode as previously described. When the ;
~, compare logic 57 eventually indicates a scan high condition, latch 119 is set and although data is transferred to main storage 10 in a manner as prev;ously described, it is not entered into main storage 10 because the block data storage signal on conductor 139 prevents data -From being written into main storage 10.
The timing diagram in Fig. 6 illustrates that data ~ buffer 40 was initially loaded with the First byte of data ; hexidecimal 00 and then with the third byte of data hexi-decimal 02. Thereafter, data buffer 40 is loaded with data which is represented by XX or a don't care condition until , 20 the Deserialize gate comes up and then it is loaded with a 1 , . .
byte from the disk data field; i.e., the first byte oF the key ID field. Thereafter, data buffer 40 is loaded with i! every other byte ln the disk data fielcl represented in Fig.
5. Similarly, data buffer 41 is loacled with a hexidecimal `I ~ .
00 which is the second byte of the search key in the scan field. lhe next byte to be loaded into data buffer 41 is .
hexidecimal FF. Data buffer 41 is then loaded with bytes represented by XX which indicates that they are not of significance during the serialize operation. However, when switching into the read mode, the Deserialize ga-te is pre- ~
sent and the second byte oF the key ID field in the disk data ~ ;
Fleld, i.e., hexidecimal 06 is entered into data buffer 41. ~ -.,~ - . ~, .~. . . .
~038so~
l The Da~a Store register 40 and the l~lrite register 55 are loaded with bytes of data from the scan field in main storage lO as shown. This -takes place during the scan operation. ;
The gate register 47 is loaded when the operation switches to a read mode. The Gate register 47 is loaded with bytes of data from the disk data field. The remaining signals in the timing diagram are signals for controlling the serialize operation, the field time signal, the load Write register control signal, the load Data Store register 50 from buffers 40 or 41 signals, the Deserialize gate signal and the load buffers 40 or 41 from gate register 47 signals.
From the foregoing it is seen that the invention com~
bines scan and read operations within a disk data field. A
search key and a distinguishing pattern are placed in the scan field whereby af-ter sensintJ the search key and upon sensing the distinguishing pattern an indication is provided for switching from the scan mode into the read mode. During the read mode, the data from the disk data field is then transferred to main storage and is entered therein only if ~;
the key of the disk data field compares low or equal to the search key of the scan field. If the key in the disk data field compares high to the storage search key, the data from ; the disk data field is still transferred but is not entered ;nto main storage because the key being sought from the disk data field must already be stored in the scan field.
. .. . . . .
:
occurred. A dummy cycle steal request is generated and sent to the Buffer Controls and Cycle Steal Controls 85. The i logic for generating the dummy cycle steal request includes - AND circuit 147 which controls the setting of Dummy Cycle ,;
Steal latch 148. AND circuit 147 has inputs for receiving the Cycle Request 1 signal, the Scan Read 1st FF signal and a clock 3 signal. The output of latch 148 is applied to OR ;
circuit 150 which also has an input for receiving the Data ,~ , . .
~ Cycle Generate signal. The output from OR circuit 150 is a ;~ signal applied to Buffer and Cycle Steal Controls 85 for in- ~`
~ dicating that Buffers 40 and 41 are full. Latch 148 is reset }
by the output of OR circuit 149. OR circuit 149 receives a clock 7 signal and a not Data Time Signal.
.; , . ..
Decode loqic 75 detects when the hexidecimal FF byte of ;~
"
~, . .
,, .
r 1 data is in the ~Irite register 55. The decode logic ~5 in res~
ponse to detecting the hexidecimal FF byte of data in Write register 55 generates a Write Reg FF signal on conductor 130 which is applied to AND circuit 109 in Fig. 2. AND circui-t 109 is also connected to receive the set output oF the Scan Read FF latch 107 and a Field Time signal on conductor 129.
The Field Time signal is a timing signal coming from attach-ment 30, see page 8-0~5 of the IBM 5445 Disk Storage Drive Attachment for System/3 Manual. AND circuit 109 provides a signal which is used -For switching from a scan mode, i.e., '! a pull mode into a read mode, i.e., a push mode. The signal , from AND circuit 109 is applied to AND circuit 113 which con- `
trols the setting of the Switch Modes latch 115. A~ID circuit 113 is gated or conditioned by a Bit Time 1 signal which comes from attachment 30 over Bit Times bus 76, Fig. lb. The bit time 1 signal in Fig. 2 is shown as being applied to conduc-tor 77 which forms a part of bus 76.
:! The set output of latch 115 is used for several purposes.
First, it is used to block buffer action request by providing a Block Buffer Action Req signal over conductor 135 to Buffer and Cycle Steal Controls 85 of Fig. la. The signal on conduc-tor 135 causes the Buffer and Cycle Steal Controls 85 to gener-ate a signal for preventing the transfer of data from either Data Buffer ~0 or ~1 to the Data Store register 50. Th;s action is necessary to prevent a data over run condition in the Buffer Control Logic 85.
~t Before the deserialized byte of data is transferred, it is necessary to reset Pull Mode. The reset signal for the Pull Mode is passed by AND circuit 117 which is connected to the set output of latch 115 and also receives a Bit Time ~ on conductor 78. The Reset Pull Mode signal from AND circuit 117 is also passed by OR circuit 120 as a Wrong Sync Restart . :
1~3~i~
or S~litch signal For resettin~J a serialize l~tch, see page 8-080 oF the IBM 5445 Disk Drive Attachment for Systeml3 `~
manual to stop the serializiny opera-tion and stopping the compare operation in the attachment 30. The Deserialize latch in the Select logic 46 of attachment 30 is se-t when `
attachment 30 receives a Switch Mode signal on conductor ~;
136, i.e., when Switch Modes latch 115 is set. The set out~
put of latch 115 is also applied to AND circuit 118 which controls the setting of the Block Data Store latch 119.
However, AND circuit 118 is condi tioned only when Compare `'' '"!. ~' logic 57 provides a scan high compare signal on conductor 137- Tn this instance, the resul ts of the compare operation are such that the scan high compare signal is not generated. ` `~
The Reset Pull Mode signal from AND circuit 117 is also used to reset the Scan Read FF latch 107 via OR circuit 106.
However, it should be noted that before latch 107 was reset latch 116 was set. The set output of latch 116 is applied ;~
to AND circuit 121 which also receives a Select Key Length signal on conductor 138. The Select Key Length signal comes from Buffer and Cycle steal controls 85, see page 8-215 of the IBM 5445 Disk Storage Drive Attachment for System/3 Manual. The output of AND circuit 121 provides a Subtract 1 ~ 1 from Disk Drive Data Register (DDDR) which is a local store register in CPU 15. The Subtract 1 from the Disk Drive Data Register (DDDR) is used to cause proper addressing of the scan field in main storage 10. The additional decrement is -., .: . ~
necessary because of one hexidecimal FF byte which is used to separate the search key from the disk data field which is placed in main storage In ~ manner which will now be described. -~
With the operation switched from the Pull Mode into the ` ,~
Read Mode and with the Deserialize Latch in Buffer and Cycle Steal Controls 85 set, a deserialized byte of clata is trans-:
:
~:
~0385~0 :~`
1 ferred from Deserializer 59 to Read Register 60 and from there through Select lo~ic 46, register 47 to Data Buffers 40 or 41.
The byte of data is then i;ransferred from data buffer 40 or 41 to DBI register 52. The byte of data in DBI register 62 is then transferred to main storage 10 via Data Bus In 63 and `3 CPU 15 at a location specified by the address in the DDDR
` register. Successive deserialized bytes of data are trans-ferred in a similar manner.
The number of bytes transferred is determined by the ~' 10 value in the Data Length register 44 during the time the ID
field was being read by the disk storage drive 200. Each time that a byte of data is transferred into main storage 10, the value in a counter in the Buffer and Cycle Steal controls 85 is decremented by 1. The operation continues until the ~, entire disk data field is transferred into main storage 10.
The data transfer is complete when the Data Time signal on , conductor 125 ls no longer present. This causes inverter 104 ;~ to provide a signal for resetting latch 107 via OR circuit 106, for resetting latch 115 vla OR circult 114 and for resetting latches 116 and 119. Latch 102 is not reset at :
this time because the scan read operation is not complete.
The scan read operation is not complete until a scan high condition has been detected or other predesignated conditions have come into being.
The operation again switches into a pull mode during the gap time preceding the next disk data field. The opera-i~ tion then continues in a manner as previously described. If ', the results of the compare operation still do not provide a -~
.i scan high compare signal on conductor 137 in Fig. 2, the newly transferred data would be entered into main storage 10 so as to overlay the data which had been entered into the ~ `~
scan field from the previous disk data field. With refer-,ii, R09-73-029 -13-:~`
~31~5~
l ence to Figs. 3 and 4, it s~ould be noted that the search ~ ;
key in the scan field is separated by a byte of hexidecimal ;
FF from the disk data field which has been en-tered into the scan field. This byte of hexidecimal FF continues to indi~
cate that the compare operation is to no longer take place and provides the necessary signals for conditioning AND~ ~ "~'!.
circuit 108 so as to initiate the switching from the pull mode into a read mode as previously described. When the ;
~, compare logic 57 eventually indicates a scan high condition, latch 119 is set and although data is transferred to main storage 10 in a manner as prev;ously described, it is not entered into main storage 10 because the block data storage signal on conductor 139 prevents data -From being written into main storage 10.
The timing diagram in Fig. 6 illustrates that data ~ buffer 40 was initially loaded with the First byte of data ; hexidecimal 00 and then with the third byte of data hexi-decimal 02. Thereafter, data buffer 40 is loaded with data which is represented by XX or a don't care condition until , 20 the Deserialize gate comes up and then it is loaded with a 1 , . .
byte from the disk data field; i.e., the first byte oF the key ID field. Thereafter, data buffer 40 is loaded with i! every other byte ln the disk data fielcl represented in Fig.
5. Similarly, data buffer 41 is loacled with a hexidecimal `I ~ .
00 which is the second byte of the search key in the scan field. lhe next byte to be loaded into data buffer 41 is .
hexidecimal FF. Data buffer 41 is then loaded with bytes represented by XX which indicates that they are not of significance during the serialize operation. However, when switching into the read mode, the Deserialize ga-te is pre- ~
sent and the second byte oF the key ID field in the disk data ~ ;
Fleld, i.e., hexidecimal 06 is entered into data buffer 41. ~ -.,~ - . ~, .~. . . .
~038so~
l The Da~a Store register 40 and the l~lrite register 55 are loaded with bytes of data from the scan field in main storage lO as shown. This -takes place during the scan operation. ;
The gate register 47 is loaded when the operation switches to a read mode. The Gate register 47 is loaded with bytes of data from the disk data field. The remaining signals in the timing diagram are signals for controlling the serialize operation, the field time signal, the load Write register control signal, the load Data Store register 50 from buffers 40 or 41 signals, the Deserialize gate signal and the load buffers 40 or 41 from gate register 47 signals.
From the foregoing it is seen that the invention com~
bines scan and read operations within a disk data field. A
search key and a distinguishing pattern are placed in the scan field whereby af-ter sensintJ the search key and upon sensing the distinguishing pattern an indication is provided for switching from the scan mode into the read mode. During the read mode, the data from the disk data field is then transferred to main storage and is entered therein only if ~;
the key of the disk data field compares low or equal to the search key of the scan field. If the key in the disk data field compares high to the storage search key, the data from ; the disk data field is still transferred but is not entered ;nto main storage because the key being sought from the disk data field must already be stored in the scan field.
. .. . . . .
Claims (7)
1. In a computer system including main storage, a central processing unit, a disk storage drive, a disk storage drive attachment for connecting said disk storage drive to said central processing unit, the improvement comprising, means for reading bytes of data from a disk data field in said disk storage drive containing data to be entered into said main storage, means for reading bytes of data from a scan field in main storage having a search key with the remaining bytes therein set to a predetermined coded value distinguishable from said search key, compare means for comparing bytes of data read From said scan field with bytes of data read from said disk data field and indicating a compare condition, decoding means responsive to the first byte of said scan field having said predetermined coded value distinguishable from said search key for generating a mode switching signal, and means responsive to said mode switching signal and a compare condition for transferring bytes of data read from said disk data field to said scan field in main storage.
2. The computer system of claim 1 wherein said compare condition is a low compare condition.
3. The computer system of claim 1 where said scan field has a length one byte greater than the length of said disk data field.
4. The computer system of claim 1 where said search key is located at the head of said scan field.
5. The computer system of claim 1 wherein the bytes from said disk data field are transferred into said scan field to be separated from said search key therein by at least one byte having said predetermined coded value distinguish-able from said search key.
6. The computer system of claim 1 wherein said predeter-mined coded value distinguishable from said search key is hexidecimal FF.
7. The computer system of claim 1 further comprising means responsive to said mode switching signal and a compare high condition for inhibiting the entry of bytes from said disk data field into said scan field.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA300,238A CA1050169A (en) | 1973-10-24 | 1978-03-31 | Scan and read control apparatus for a disk storage drive in a computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US00409215A US3848235A (en) | 1973-10-24 | 1973-10-24 | Scan and read control apparatus for a disk storage drive in a computer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1038500A true CA1038500A (en) | 1978-09-12 |
Family
ID=23619529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA209,551A Expired CA1038500A (en) | 1973-10-24 | 1974-09-19 | Scan and read control apparatus for a disk storage drive in a computer system |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US3848235A (en) |
| CA (1) | CA1038500A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3431558A (en) * | 1966-08-04 | 1969-03-04 | Ibm | Data storage system employing an improved indexing technique therefor |
| US3601808A (en) * | 1968-07-18 | 1971-08-24 | Bell Telephone Labor Inc | Advanced keyword associative access memory system |
| US3611314A (en) * | 1969-09-09 | 1971-10-05 | Texas Instruments Inc | Dynamic associative data processing system |
| BE759562A (en) * | 1969-12-31 | 1971-04-30 | Ibm | AUXILIARY STORAGE DEVICE AND IMPLEMENTATION METHOD |
| US3647348A (en) * | 1970-01-19 | 1972-03-07 | Fairchild Camera Instr Co | Hardware-oriented paging control system |
| US3668647A (en) * | 1970-06-12 | 1972-06-06 | Ibm | File access system |
| US3792442A (en) * | 1970-10-30 | 1974-02-12 | Mobil Oil Corp | Apparatus for controlling the transfer of data from core to disc storage in a video display system |
| US3689891A (en) * | 1970-11-02 | 1972-09-05 | Texas Instruments Inc | Memory system |
| US3781812A (en) * | 1971-06-28 | 1973-12-25 | Burroughs Corp | Addressing system responsive to a transfer vector for accessing a memory |
-
1973
- 1973-10-24 US US00409215A patent/US3848235A/en not_active Expired - Lifetime
-
1974
- 1974-09-19 CA CA209,551A patent/CA1038500A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3848235A (en) | 1974-11-12 |
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